DE69015371D1 - Lese-/schreibe-/wiederherstellungsschaltung für speichermatrizen. - Google Patents

Lese-/schreibe-/wiederherstellungsschaltung für speichermatrizen.

Info

Publication number
DE69015371D1
DE69015371D1 DE69015371T DE69015371T DE69015371D1 DE 69015371 D1 DE69015371 D1 DE 69015371D1 DE 69015371 T DE69015371 T DE 69015371T DE 69015371 T DE69015371 T DE 69015371T DE 69015371 D1 DE69015371 D1 DE 69015371D1
Authority
DE
Germany
Prior art keywords
write
read
recovery circuit
memory matrices
matrices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69015371T
Other languages
English (en)
Other versions
DE69015371T2 (de
Inventor
Frank Montegari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69015371D1 publication Critical patent/DE69015371D1/de
Publication of DE69015371T2 publication Critical patent/DE69015371T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
DE69015371T 1990-05-17 1990-10-15 Lese-/schreibe-/wiederherstellungsschaltung für speichermatrizen. Expired - Fee Related DE69015371T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US52528690A 1990-05-17 1990-05-17
PCT/US1990/005897 WO1991018394A1 (en) 1990-05-17 1990-10-15 Read/write/restore circuit for memory arrays

Publications (2)

Publication Number Publication Date
DE69015371D1 true DE69015371D1 (de) 1995-02-02
DE69015371T2 DE69015371T2 (de) 1995-07-13

Family

ID=24092639

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69015371T Expired - Fee Related DE69015371T2 (de) 1990-05-17 1990-10-15 Lese-/schreibe-/wiederherstellungsschaltung für speichermatrizen.

Country Status (5)

Country Link
US (1) US5465230A (de)
EP (1) EP0528799B1 (de)
JP (1) JPH0770221B2 (de)
DE (1) DE69015371T2 (de)
WO (1) WO1991018394A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5894434A (en) * 1995-12-22 1999-04-13 Texas Instruments Incorporated MOS static memory array
KR100349371B1 (ko) * 1999-11-30 2002-08-21 주식회사 하이닉스반도체 반도체 메모리 장치의 프리페치/리스토어 방법 및 그 회로
US10510401B2 (en) * 2017-05-22 2019-12-17 Taiwan Semicondutor Manufacturing Company Limited Semiconductor memory device using shared data line for read/write operation

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5484936A (en) * 1977-12-20 1979-07-06 Fujitsu Ltd Decoder circuit
US4208730A (en) * 1978-08-07 1980-06-17 Rca Corporation Precharge circuit for memory array
JPS56500108A (de) * 1979-03-13 1981-02-05
JPS56101694A (en) * 1980-01-18 1981-08-14 Nec Corp Semiconductor circuit
JPS589285A (ja) * 1981-07-08 1983-01-19 Toshiba Corp 半導体装置
JPS5968889A (ja) * 1982-10-08 1984-04-18 Toshiba Corp 半導体記憶装置
US4531068A (en) * 1983-09-19 1985-07-23 International Business Machines Corporation Bus line precharging tristate driver circuit
JPS6066389A (ja) * 1983-09-22 1985-04-16 Fujitsu Ltd 半導体記憶装置
JPS60136989A (ja) * 1983-12-26 1985-07-20 Hitachi Ltd 半導体記憶装置の書き込み回路
JPS60177723A (ja) * 1984-02-24 1985-09-11 Hitachi Ltd 出力回路
JPS613390A (ja) * 1984-06-15 1986-01-09 Hitachi Ltd 記憶装置
US4644196A (en) * 1985-01-28 1987-02-17 Motorola, Inc. Tri-state differential amplifier
KR860006875A (ko) * 1985-02-25 1986-09-15 미쓰다 가쓰시게 반도체 장치
US4730279A (en) * 1985-03-30 1988-03-08 Kabushiki Kaisha Toshiba Static semiconductor memory device
US4636990A (en) * 1985-05-31 1987-01-13 International Business Machines Corporation Three state select circuit for use in a data processing system or the like
JP2532831B2 (ja) * 1985-06-03 1996-09-11 日本電信電話株式会社 メモリ回路
US4658381A (en) * 1985-08-05 1987-04-14 Motorola, Inc. Bit line precharge on a column address change
US4686396A (en) * 1985-08-26 1987-08-11 Xerox Corporation Minimum delay high speed bus driver
JPS62145595A (ja) * 1985-12-20 1987-06-29 Toshiba Corp 半導体記憶装置
US4678940A (en) * 1986-01-08 1987-07-07 Advanced Micro Devices, Inc. TTL compatible merged bipolar/CMOS output buffer circuits
JPH0640439B2 (ja) * 1986-02-17 1994-05-25 日本電気株式会社 半導体記憶装置
US4752913A (en) * 1986-04-30 1988-06-21 International Business Machines Corporation Random access memory employing complementary transistor switch (CTS) memory cells
EP0258715B1 (de) * 1986-08-15 1994-06-08 Nec Corporation Statischer Direktzugriffspeicher einer Bi-CMOS-Konstruktion
NL8602295A (nl) * 1986-09-11 1988-04-05 Philips Nv Halfgeleidergeheugenschakeling met snelle uitleesversterker tristatebusdrijver.
JPS63104290A (ja) * 1986-10-21 1988-05-09 Nec Corp 半導体記憶装置
US4825413A (en) * 1987-02-24 1989-04-25 Texas Instruments Incorporated Bipolar-CMOS static ram memory device
US4961168A (en) * 1987-02-24 1990-10-02 Texas Instruments Incorporated Bipolar-CMOS static random access memory device with bit line bias control
JPS6425394A (en) * 1987-07-21 1989-01-27 Mitsubishi Electric Corp Nonvolatile semiconductor memory device
US4882507B1 (en) * 1987-07-31 1993-03-16 Output circuit of semiconductor integrated circuit device
US4853898A (en) * 1988-02-11 1989-08-01 Digital Equipment Corporation Bipolar ram having state dependent write current
US4862421A (en) * 1988-02-16 1989-08-29 Texas Instruments Incorporated Sensing and decoding scheme for a BiCMOS read/write memory
US4866674A (en) * 1988-02-16 1989-09-12 Texas Instruments Incorporated Bitline pull-up circuit for a BiCMOS read/write memory
US4967102A (en) * 1989-06-08 1990-10-30 Texas Instruments Incorporated BiCMOS power up 3-state circuit having no through current in the disabled mode

Also Published As

Publication number Publication date
JPH0770221B2 (ja) 1995-07-31
EP0528799A1 (de) 1993-03-03
DE69015371T2 (de) 1995-07-13
WO1991018394A1 (en) 1991-11-28
EP0528799B1 (de) 1994-12-21
JPH05507169A (ja) 1993-10-14
US5465230A (en) 1995-11-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee