DE69012848D1 - Integrierte Halbleiterschaltungsanordnungen. - Google Patents

Integrierte Halbleiterschaltungsanordnungen.

Info

Publication number
DE69012848D1
DE69012848D1 DE69012848T DE69012848T DE69012848D1 DE 69012848 D1 DE69012848 D1 DE 69012848D1 DE 69012848 T DE69012848 T DE 69012848T DE 69012848 T DE69012848 T DE 69012848T DE 69012848 D1 DE69012848 D1 DE 69012848D1
Authority
DE
Germany
Prior art keywords
semiconductor circuit
integrated semiconductor
circuit arrangements
arrangements
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69012848T
Other languages
English (en)
Other versions
DE69012848T2 (de
Inventor
Shigeru Moriuchi
Masashi Takeda
Takayuki Mogi
Hiroaki Anmo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP1030579A external-priority patent/JPH02209750A/ja
Priority claimed from JP1030578A external-priority patent/JP2850345B2/ja
Priority claimed from JP1031977A external-priority patent/JP2797371B2/ja
Priority claimed from JP1037003A external-priority patent/JPH02215152A/ja
Application filed by Sony Corp filed Critical Sony Corp
Application granted granted Critical
Publication of DE69012848D1 publication Critical patent/DE69012848D1/de
Publication of DE69012848T2 publication Critical patent/DE69012848T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11801—Masterslice integrated circuits using bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11896—Masterslice integrated circuits using combined field effect/bipolar technology
DE69012848T 1989-02-09 1990-02-02 Integrierte Halbleiterschaltungsanordnungen. Expired - Fee Related DE69012848T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP1030579A JPH02209750A (ja) 1989-02-09 1989-02-09 マスタスライス方式の半導体集積回路装置
JP1030578A JP2850345B2 (ja) 1989-02-09 1989-02-09 マスタスライス方式の半導体集積回路装置
JP1031977A JP2797371B2 (ja) 1989-02-10 1989-02-10 マスタスライス方式の半導体集積回路装置及びその製造方法
JP1037003A JPH02215152A (ja) 1989-02-16 1989-02-16 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69012848D1 true DE69012848D1 (de) 1994-11-03
DE69012848T2 DE69012848T2 (de) 1995-03-09

Family

ID=27459281

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69012848T Expired - Fee Related DE69012848T2 (de) 1989-02-09 1990-02-02 Integrierte Halbleiterschaltungsanordnungen.

Country Status (3)

Country Link
US (1) US5101258A (de)
EP (1) EP0382415B1 (de)
DE (1) DE69012848T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04352467A (ja) * 1991-05-30 1992-12-07 Toshiba Corp Ｍｏｓ型半導体集積回路装置
US5440153A (en) * 1994-04-01 1995-08-08 United Technologies Corporation Array architecture with enhanced routing for linear asics
US20060081971A1 (en) * 1997-09-30 2006-04-20 Jeng Jye Shau Signal transfer methods for integrated circuits
JP2003045880A (ja) * 2001-07-31 2003-02-14 Mitsubishi Electric Corp 半導体装置及び半導体装置の製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5887854A (ja) * 1981-11-20 1983-05-25 Nec Corp マスタスライス方式ｌｓｉ基板
JPH0669142B2 (ja) * 1983-04-15 1994-08-31 株式会社日立製作所 半導体集積回路装置
US4579600A (en) * 1983-06-17 1986-04-01 Texas Instruments Incorporated Method of making zero temperature coefficient of resistance resistors
JPS6035532A (ja) * 1983-07-29 1985-02-23 Fujitsu Ltd マスタスライス集積回路装置
JPS6074455A (ja) * 1983-09-29 1985-04-26 Fujitsu Ltd マスタスライス集積回路
JPS6289341A (ja) * 1985-10-15 1987-04-23 Mitsubishi Electric Corp マスタスライス方式大規模半導体集積回路装置の製造方法
JPS62219555A (ja) * 1986-03-19 1987-09-26 Fuji Electric Co Ltd バイポ−ラ・ｍｏｓ半導体装置
JPH0654795B2 (ja) * 1986-04-07 1994-07-20 三菱電機株式会社 半導体集積回路装置及びその製造方法
JPS62263671A (ja) * 1986-05-09 1987-11-16 Matsushita Electric Ind Co Ltd 半導体集積回路
JPS6380559A (ja) * 1986-09-24 1988-04-11 Fuji Electric Co Ltd バイポ−ラ・ｃｍｏｓ半導体装置
JPS63186462A (ja) * 1987-01-28 1988-08-02 Mitsubishi Electric Corp 半導体集積回路
GB8726366D0 (en) * 1987-11-11 1987-12-16 Lsi Logic Ltd Ic array

Also Published As

Publication number Publication date
DE69012848T2 (de) 1995-03-09
EP0382415A2 (de) 1990-08-16
EP0382415B1 (de) 1994-09-28
EP0382415A3 (de) 1991-04-10
US5101258A (en) 1992-03-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee