DE68927147D1 - Prüfgerät und -verfahren zur Prüfung eines elektronischen Geräts und Halbleitergerät mit diesem Prüfgerät - Google Patents

Prüfgerät und -verfahren zur Prüfung eines elektronischen Geräts und Halbleitergerät mit diesem Prüfgerät

Info

Publication number
DE68927147D1
DE68927147D1 DE68927147T DE68927147T DE68927147D1 DE 68927147 D1 DE68927147 D1 DE 68927147D1 DE 68927147 T DE68927147 T DE 68927147T DE 68927147 T DE68927147 T DE 68927147T DE 68927147 D1 DE68927147 D1 DE 68927147D1
Authority
DE
Germany
Prior art keywords
electronic device
output signal
test
comparators
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68927147T
Other languages
English (en)
Other versions
DE68927147T2 (de
Inventor
Koichiro Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE68927147D1 publication Critical patent/DE68927147D1/de
Application granted granted Critical
Publication of DE68927147T2 publication Critical patent/DE68927147T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
DE68927147T 1988-10-28 1989-10-25 Prüfgerät und -verfahren zur Prüfung eines elektronischen Geräts und Halbleitergerät mit diesem Prüfgerät Expired - Fee Related DE68927147T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63272166A JPH02118474A (ja) 1988-10-28 1988-10-28 伝播遅延時間の試験装置

Publications (2)

Publication Number Publication Date
DE68927147D1 true DE68927147D1 (de) 1996-10-17
DE68927147T2 DE68927147T2 (de) 1997-01-23

Family

ID=17510001

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68927147T Expired - Fee Related DE68927147T2 (de) 1988-10-28 1989-10-25 Prüfgerät und -verfahren zur Prüfung eines elektronischen Geräts und Halbleitergerät mit diesem Prüfgerät

Country Status (5)

Country Link
US (1) US5053698A (de)
EP (1) EP0366553B1 (de)
JP (1) JPH02118474A (de)
KR (1) KR930001547B1 (de)
DE (1) DE68927147T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3253296B2 (ja) * 1989-12-20 2002-02-04 セイコーエプソン株式会社 記憶装置及びデータ処理装置
JPH045583A (ja) * 1990-04-23 1992-01-09 Ando Electric Co Ltd データログ回路
US5550845A (en) * 1990-08-03 1996-08-27 Siemens Aktiengesellschaft Method for dynamic testing of digital logic circuits
US5258986A (en) * 1990-09-19 1993-11-02 Vlsi Technology, Inc. Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories
JP2765771B2 (ja) * 1991-08-07 1998-06-18 ローム株式会社 半導体記憶装置の試験方法
US5422852A (en) * 1992-02-27 1995-06-06 Texas Instruments Incorporated Method and system for screening logic circuits
JPH063424A (ja) * 1992-06-22 1994-01-11 Mitsubishi Electric Corp 集積回路装置、および集積回路装置に組込まれるテストデータ発生回路
US5363038A (en) * 1992-08-12 1994-11-08 Fujitsu Limited Method and apparatus for testing an unpopulated chip carrier using a module test card
US5477160A (en) * 1992-08-12 1995-12-19 Fujitsu Limited Module test card
US5528602A (en) * 1992-12-30 1996-06-18 International Business Machines Corporation Method for determining computer subsystem property
US5381419A (en) * 1993-03-01 1995-01-10 At&T Corp. Method and apparatus for detecting retention faults in memories
US5956280A (en) * 1998-03-02 1999-09-21 Tanisys Technology, Inc. Contact test method and system for memory testers
JP2000021193A (ja) * 1998-07-01 2000-01-21 Fujitsu Ltd メモリ試験方法及び装置並びに記憶媒体
DE19845409A1 (de) * 1998-10-02 2000-04-20 Ibm Schnelle Bestimmung des Flush-Delays bei Chips mit LSSD-Design
WO2002103379A1 (fr) * 2001-06-13 2002-12-27 Advantest Corporation Instrument destine a tester des dispositifs semi-conducteurs et procede destine a tester des dispositifs semi-conducteurs
US7385385B2 (en) * 2001-10-03 2008-06-10 Nextest Systems Corporation System for testing DUT and tester for use therewith
US6868212B2 (en) * 2003-03-06 2005-03-15 Evans & Sutherland Computer Corporation Method and apparatus for controlling wavelength and dominant mode in fiber lasers
US7461304B1 (en) 2003-07-07 2008-12-02 Marvell Israel (M.I.S.L.) Ltd. Integrated circuit test using clock signal modification
JP2007010606A (ja) * 2005-07-04 2007-01-18 Matsushita Electric Ind Co Ltd Ｌｓｉ検査モジュール、ｌｓｉ検査モジュールの制御方法、ｌｓｉ検査モジュールとｌｓｉ検査装置との通信方法、およびｌｓｉ検査方法
US7891818B2 (en) 2006-12-12 2011-02-22 Evans & Sutherland Computer Corporation System and method for aligning RGB light in a single modulator projector
US8358317B2 (en) 2008-05-23 2013-01-22 Evans & Sutherland Computer Corporation System and method for displaying a planar image on a curved surface
US8702248B1 (en) 2008-06-11 2014-04-22 Evans & Sutherland Computer Corporation Projection method for reducing interpixel gaps on a viewing surface
US8077378B1 (en) 2008-11-12 2011-12-13 Evans & Sutherland Computer Corporation Calibration system and method for light modulation device
DE102009010886B4 (de) * 2009-02-27 2013-06-20 Advanced Micro Devices, Inc. Erkennung der Verzögerungszeit in einem eingebauten Speicherselbsttest unter Anwendung eines Ping-Signals
US9641826B1 (en) 2011-10-06 2017-05-02 Evans & Sutherland Computer Corporation System and method for displaying distant 3-D stereo on a dome surface

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1278694A (en) * 1969-07-04 1972-06-21 Sperry Rand Corp Improvements in or relating to apparatus for testing electronic circuits
JPS5832178A (ja) * 1981-08-19 1983-02-25 Advantest Corp Ｉｃテスタ
JPS59176892A (ja) * 1983-03-26 1984-10-06 富士ファコム制御株式会社 アナログデ−タ収集方式
US4710932A (en) * 1986-01-15 1987-12-01 Kashiwagi Hiroshi Method of and apparatus for fault detection in digital circuits by comparison of test signals applied to a test circuit and a faultless reference circuit
JPS647400A (en) * 1987-06-29 1989-01-11 Hitachi Ltd Ic tester

Also Published As

Publication number Publication date
JPH02118474A (ja) 1990-05-02
EP0366553B1 (de) 1996-09-11
US5053698A (en) 1991-10-01
DE68927147T2 (de) 1997-01-23
EP0366553A2 (de) 1990-05-02
EP0366553A3 (de) 1991-10-23
KR930001547B1 (ko) 1993-03-04
KR900006789A (ko) 1990-05-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee