DE3686989D1 - Verminderung des rauschens waehrend des pruefens von integrierten schaltungschips. - Google Patents

Verminderung des rauschens waehrend des pruefens von integrierten schaltungschips.

Info

Publication number
DE3686989D1
DE3686989D1 DE8686110981T DE3686989T DE3686989D1 DE 3686989 D1 DE3686989 D1 DE 3686989D1 DE 8686110981 T DE8686110981 T DE 8686110981T DE 3686989 T DE3686989 T DE 3686989T DE 3686989 D1 DE3686989 D1 DE 3686989D1
Authority
DE
Germany
Prior art keywords
integrated circuit
tester
circuit device
test system
reducing noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686110981T
Other languages
English (en)
Other versions
DE3686989T2 (de
Inventor
Evan E Davidson
David A Kiesling
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3686989D1 publication Critical patent/DE3686989D1/de
Publication of DE3686989T2 publication Critical patent/DE3686989T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31924—Voltage or current aspects, e.g. driver, receiver
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE8686110981T 1985-09-03 1986-08-08 Verminderung des rauschens waehrend des pruefens von integrierten schaltungschips. Expired - Fee Related DE3686989T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/771,928 US4644265A (en) 1985-09-03 1985-09-03 Noise reduction during testing of integrated circuit chips

Publications (2)

Publication Number Publication Date
DE3686989D1 true DE3686989D1 (de) 1992-11-26
DE3686989T2 DE3686989T2 (de) 1993-04-22

Family

ID=25093363

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686110981T Expired - Fee Related DE3686989T2 (de) 1985-09-03 1986-08-08 Verminderung des rauschens waehrend des pruefens von integrierten schaltungschips.

Country Status (4)

Country Link
US (1) US4644265A (de)
EP (1) EP0213453B1 (de)
JP (1) JPH0762695B2 (de)
DE (1) DE3686989T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5046048A (en) * 1988-07-15 1991-09-03 Kabushiki Kaisha Toshiba Semiconductor integrated circuit including output buffer
US4973904A (en) * 1988-12-12 1990-11-27 Ncr Corporation Test circuit and method
US5289118A (en) * 1991-02-01 1994-02-22 Data I/O Corporation Programmer/tester with electronically switched bypass capacitor
US5142167A (en) * 1991-05-01 1992-08-25 International Business Machines Corporation Encoding for simultaneous switching output noise reduction
US5463315A (en) * 1993-06-15 1995-10-31 Hewlett-Packard Company Spike suppression for a tester circuit for integrated circuits
US5504423A (en) * 1994-11-01 1996-04-02 The Research Foundation Of State University Of New York Method for modeling interactions in multilayered electronic packaging structures
US5477460A (en) * 1994-12-21 1995-12-19 International Business Machines Corporation Early high level net based analysis of simultaneous switching
US5572736A (en) * 1995-03-31 1996-11-05 International Business Machines Corporation Method and apparatus for reducing bus noise and power consumption
US5663966A (en) * 1996-07-24 1997-09-02 International Business Machines Corporation System and method for minimizing simultaneous switching during scan-based testing
JP4652729B2 (ja) * 2004-06-28 2011-03-16 富士通セミコンダクター株式会社 半導体装置
US20080046789A1 (en) * 2006-08-21 2008-02-21 Igor Arsovski Apparatus and method for testing memory devices and circuits in integrated circuits

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3599161A (en) * 1969-04-03 1971-08-10 Computer Test Corp Computer controlled test system and method
US3694632A (en) * 1969-12-31 1972-09-26 Hawker Siddeley Dynamics Ltd Automatic test equipment utilizing a matrix of digital differential analyzer integrators to generate interrogation signals
US3784910A (en) * 1972-07-13 1974-01-08 Teradyne Inc Sequential addressing network testing system
US3789205A (en) * 1972-09-28 1974-01-29 Ibm Method of testing mosfet planar boards
FR2330014A1 (fr) * 1973-05-11 1977-05-27 Ibm France Procede de test de bloc de circuits logiques integres et blocs en faisant application
US3848188A (en) * 1973-09-10 1974-11-12 Probe Rite Inc Multiplexer control system for a multi-array test probe assembly
US3873818A (en) * 1973-10-29 1975-03-25 Ibm Electronic tester for testing devices having a high circuit density
US3961251A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US3976940A (en) * 1975-02-25 1976-08-24 Fairchild Camera And Instrument Corporation Testing circuit
US4066882A (en) * 1976-08-16 1978-01-03 Grumman Aerospace Corporation Digital stimulus generating and response measuring means
US4070565A (en) * 1976-08-18 1978-01-24 Zehntel, Inc. Programmable tester method and apparatus
US4125763A (en) * 1977-07-15 1978-11-14 Fluke Trendar Corporation Automatic tester for microprocessor board
US4180203A (en) * 1977-09-30 1979-12-25 Westinghouse Electric Corp. Programmable test point selector circuit
US4216539A (en) * 1978-05-05 1980-08-05 Zehntel, Inc. In-circuit digital tester
DE2842750A1 (de) * 1978-09-30 1980-04-10 Ibm Deutschland Verfahren und anordnung zur pruefung von durch monolithisch integrierten halbleiterschaltungen dargestellten sequentiellen schaltungen
US4348759A (en) * 1979-12-17 1982-09-07 International Business Machines Corporation Automatic testing of complex semiconductor components with test equipment having less channels than those required by the component under test
US4334310A (en) * 1980-06-23 1982-06-08 International Business Machines Corporation Noise suppressing bilevel data signal driver circuit arrangement
US4398106A (en) * 1980-12-19 1983-08-09 International Business Machines Corporation On-chip Delta-I noise clamping circuit
US4494066A (en) * 1981-07-02 1985-01-15 International Business Machines Corporation Method of electrically testing a packaging structure having n interconnected integrated circuit chips
US4504784A (en) * 1981-07-02 1985-03-12 International Business Machines Corporation Method of electrically testing a packaging structure having N interconnected integrated circuit chips
US4441075A (en) * 1981-07-02 1984-04-03 International Business Machines Corporation Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection
US4551838A (en) * 1983-06-20 1985-11-05 At&T Bell Laboratories Self-testing digital circuits
US4553049A (en) * 1983-10-07 1985-11-12 International Business Machines Corporation Oscillation prevention during testing of integrated circuit logic chips
JPS60187871A (ja) * 1984-03-07 1985-09-25 Mitsubishi Electric Corp 論理集積回路

Also Published As

Publication number Publication date
US4644265A (en) 1987-02-17
JPS6291873A (ja) 1987-04-27
EP0213453A3 (en) 1989-03-29
EP0213453A2 (de) 1987-03-11
EP0213453B1 (de) 1992-10-21
DE3686989T2 (de) 1993-04-22
JPH0762695B2 (ja) 1995-07-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee