DE69430304T2 - Anordnung zum testen von verbindungen mit pulling-widerständen - Google Patents
Anordnung zum testen von verbindungen mit pulling-widerständenInfo
- Publication number
- DE69430304T2 DE69430304T2 DE69430304T DE69430304T DE69430304T2 DE 69430304 T2 DE69430304 T2 DE 69430304T2 DE 69430304 T DE69430304 T DE 69430304T DE 69430304 T DE69430304 T DE 69430304T DE 69430304 T2 DE69430304 T2 DE 69430304T2
- Authority
- DE
- Germany
- Prior art keywords
- connections
- test
- arrangement
- pulling
- testing connections
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318544—Scanning methods, algorithms and patterns
- G01R31/31855—Interconnection testing, e.g. crosstalk, shortcircuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP93203604 | 1993-12-21 | ||
PCT/IB1994/000411 WO1995017682A1 (en) | 1993-12-21 | 1994-12-12 | Device for testing connections provided with pulling resistors |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69430304D1 DE69430304D1 (de) | 2002-05-08 |
DE69430304T2 true DE69430304T2 (de) | 2002-10-24 |
Family
ID=8214229
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69430304T Expired - Fee Related DE69430304T2 (de) | 1993-12-21 | 1994-12-12 | Anordnung zum testen von verbindungen mit pulling-widerständen |
Country Status (9)
Country | Link |
---|---|
US (1) | US5680407A (de) |
EP (1) | EP0685075B1 (de) |
JP (1) | JP3555953B2 (de) |
KR (1) | KR100362070B1 (de) |
DE (1) | DE69430304T2 (de) |
MY (1) | MY122556A (de) |
SG (1) | SG52753A1 (de) |
TW (1) | TW353142B (de) |
WO (1) | WO1995017682A1 (de) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19622009A1 (de) * | 1996-05-31 | 1997-12-04 | Siemens Ag | Testverfahren zur Prüfung von Baugruppenverbindungen |
US5802074A (en) * | 1996-09-19 | 1998-09-01 | Intel Corporation | Method and apparatus for the non-invasive testing of printed circuit board assemblies |
US5796639A (en) * | 1996-09-19 | 1998-08-18 | Intel Corporation | Method and apparatus for verifying the installation of strapping devices on a circuit board assembly |
KR100521323B1 (ko) * | 1998-04-25 | 2006-01-12 | 삼성전자주식회사 | 볼 핀을 구비하는 반도체 메모리 장치의 제이텍회로 |
GB9810512D0 (en) * | 1998-05-15 | 1998-07-15 | Sgs Thomson Microelectronics | Detecting communication errors across a chip boundary |
US6777970B2 (en) * | 2001-04-19 | 2004-08-17 | Intel Corporation | AC testing of leakage current in integrated circuits using RC time constant |
CN102165328A (zh) * | 2008-09-26 | 2011-08-24 | Nxp股份有限公司 | 用于测试部分地组装的多管芯器件的方法、集成电路管芯和多管芯器件 |
FR3093072B1 (fr) | 2019-02-26 | 2022-03-18 | Wezico | Poignée avec dispositif indicateur de changement de direction rétractable et système communicant multicanal |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4651084A (en) * | 1985-01-04 | 1987-03-17 | Rca Corporation | Fault test apparatus for conductors of multiconductor cable |
NL8502476A (nl) * | 1985-09-11 | 1987-04-01 | Philips Nv | Werkwijze voor het testen van dragers met meerdere digitaal-werkende geintegreerde schakelingen, drager voorzien van zulke schakelingen, geintegreerde schakeling geschikt voor het aanbrengen op zo'n drager, en testinrichting voor het testen van zulke dragers. |
JP2513904B2 (ja) * | 1990-06-12 | 1996-07-10 | 株式会社東芝 | テスト容易化回路 |
US5172377A (en) * | 1990-09-07 | 1992-12-15 | Genrad, Inc. | Method for testing mixed scan and non-scan circuitry |
JP3226293B2 (ja) * | 1991-04-24 | 2001-11-05 | 株式会社日立製作所 | 半導体集積回路 |
US5366906A (en) * | 1992-10-16 | 1994-11-22 | Martin Marietta Corporation | Wafer level integration and testing |
US5450415A (en) * | 1992-11-25 | 1995-09-12 | Matsushita Electric Industrial Co., Ltd. | Boundary scan cell circuit and boundary scan test circuit |
US5379302A (en) * | 1993-04-02 | 1995-01-03 | National Semiconductor Corporation | ECL test access port with low power control |
-
1994
- 1994-12-12 DE DE69430304T patent/DE69430304T2/de not_active Expired - Fee Related
- 1994-12-12 JP JP51729695A patent/JP3555953B2/ja not_active Expired - Fee Related
- 1994-12-12 WO PCT/IB1994/000411 patent/WO1995017682A1/en active IP Right Grant
- 1994-12-12 KR KR1019950703542A patent/KR100362070B1/ko not_active IP Right Cessation
- 1994-12-12 SG SG1996008955A patent/SG52753A1/en unknown
- 1994-12-12 EP EP95901570A patent/EP0685075B1/de not_active Expired - Lifetime
- 1994-12-19 MY MYPI94003411A patent/MY122556A/en unknown
- 1994-12-20 US US08/359,369 patent/US5680407A/en not_active Expired - Fee Related
-
1995
- 1995-01-25 TW TW084100664A patent/TW353142B/zh active
Also Published As
Publication number | Publication date |
---|---|
KR100362070B1 (ko) | 2003-02-11 |
MY122556A (en) | 2006-04-29 |
EP0685075A1 (de) | 1995-12-06 |
DE69430304D1 (de) | 2002-05-08 |
SG52753A1 (en) | 1998-09-28 |
JP3555953B2 (ja) | 2004-08-18 |
JPH08507610A (ja) | 1996-08-13 |
WO1995017682A1 (en) | 1995-06-29 |
TW353142B (en) | 1999-02-21 |
EP0685075B1 (de) | 2002-04-03 |
KR960701373A (ko) | 1996-02-24 |
US5680407A (en) | 1997-10-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |