DE68919155T2 - Halbleiterspeicheranordnung mit verschiedenen Substrat-Vorspannungsschaltungen. - Google Patents
Halbleiterspeicheranordnung mit verschiedenen Substrat-Vorspannungsschaltungen.Info
- Publication number
- DE68919155T2 DE68919155T2 DE68919155T DE68919155T DE68919155T2 DE 68919155 T2 DE68919155 T2 DE 68919155T2 DE 68919155 T DE68919155 T DE 68919155T DE 68919155 T DE68919155 T DE 68919155T DE 68919155 T2 DE68919155 T2 DE 68919155T2
- Authority
- DE
- Germany
- Prior art keywords
- memory device
- semiconductor memory
- substrate bias
- bias circuits
- various substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
- G11C5/146—Substrate bias generators
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63200494A JPH0724298B2 (ja) | 1988-08-10 | 1988-08-10 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68919155D1 DE68919155D1 (de) | 1994-12-08 |
DE68919155T2 true DE68919155T2 (de) | 1995-06-08 |
Family
ID=16425255
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE68919155T Expired - Lifetime DE68919155T2 (de) | 1988-08-10 | 1989-08-09 | Halbleiterspeicheranordnung mit verschiedenen Substrat-Vorspannungsschaltungen. |
Country Status (5)
Country | Link |
---|---|
US (1) | US5022005A (de) |
EP (1) | EP0354784B1 (de) |
JP (1) | JPH0724298B2 (de) |
KR (1) | KR940006993B1 (de) |
DE (1) | DE68919155T2 (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2626160B2 (ja) * | 1990-04-27 | 1997-07-02 | 日本電気株式会社 | 半導体メモリ |
DE69028625T2 (de) * | 1990-06-12 | 1997-01-30 | Fujitsu Ltd | Dynamische Speichereinrichtung mit wahlfreiem Zugriff |
US5159206A (en) * | 1990-07-31 | 1992-10-27 | Tsay Ching Yuh | Power up reset circuit |
JP2724919B2 (ja) * | 1991-02-05 | 1998-03-09 | 三菱電機株式会社 | 基板バイアス発生装置 |
JPH04255989A (ja) * | 1991-02-07 | 1992-09-10 | Mitsubishi Electric Corp | 半導体記憶装置および内部電圧発生方法 |
JP3313383B2 (ja) * | 1991-06-27 | 2002-08-12 | 日本電気株式会社 | 読み出し専用記憶装置 |
DE69328743T2 (de) * | 1992-03-30 | 2000-09-07 | Mitsubishi Electric Corp | Halbleiteranordnung |
KR950006067Y1 (ko) * | 1992-10-08 | 1995-07-27 | 문정환 | 반도체 메모리 장치 |
US6031411A (en) | 1993-06-28 | 2000-02-29 | Texas Instruments Incorporated | Low power substrate bias circuit |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5590139A (en) * | 1978-12-27 | 1980-07-08 | Fujitsu Ltd | Substrate bias generating circuit |
JPS58114392A (ja) * | 1981-12-07 | 1983-07-07 | Fujitsu Ltd | 半導体記憶装置 |
US4760560A (en) * | 1985-08-30 | 1988-07-26 | Kabushiki Kaisha Toshiba | Random access memory with resistance to crystal lattice memory errors |
JPH01278059A (ja) * | 1988-04-28 | 1989-11-08 | Nec Corp | 半導体集積回路装置 |
-
1988
- 1988-08-10 JP JP63200494A patent/JPH0724298B2/ja not_active Expired - Lifetime
-
1989
- 1989-08-09 DE DE68919155T patent/DE68919155T2/de not_active Expired - Lifetime
- 1989-08-09 KR KR1019890011313A patent/KR940006993B1/ko not_active IP Right Cessation
- 1989-08-09 EP EP89308106A patent/EP0354784B1/de not_active Expired - Lifetime
- 1989-08-10 US US07/391,891 patent/US5022005A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR900003886A (ko) | 1990-03-27 |
US5022005A (en) | 1991-06-04 |
EP0354784A3 (de) | 1991-12-11 |
JPH0724298B2 (ja) | 1995-03-15 |
EP0354784B1 (de) | 1994-11-02 |
EP0354784A2 (de) | 1990-02-14 |
KR940006993B1 (ko) | 1994-08-03 |
DE68919155D1 (de) | 1994-12-08 |
JPH0249461A (ja) | 1990-02-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: NEC CORP., TOKIO/TOKYO, JP Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |