DE68911815D1 - Halbleiteranordnung mit verbesserter Elementisolierungsfläche. - Google Patents

Halbleiteranordnung mit verbesserter Elementisolierungsfläche.

Info

Publication number
DE68911815D1
DE68911815D1 DE89113245T DE68911815T DE68911815D1 DE 68911815 D1 DE68911815 D1 DE 68911815D1 DE 89113245 T DE89113245 T DE 89113245T DE 68911815 T DE68911815 T DE 68911815T DE 68911815 D1 DE68911815 D1 DE 68911815D1
Authority
DE
Germany
Prior art keywords
element isolation
isolation area
semiconductor arrangement
improved element
improved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE89113245T
Other languages
English (en)
Other versions
DE68911815T2 (de
Inventor
Takashi C O Intellectual Arai
Nakafumi C O Intellectua Inada
Tsutomu Intellectual Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE68911815D1 publication Critical patent/DE68911815D1/de
Publication of DE68911815T2 publication Critical patent/DE68911815T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE68911815T 1988-09-27 1989-07-19 Halbleiteranordnung mit verbesserter Elementisolierungsfläche. Expired - Fee Related DE68911815T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63241501A JPH0691250B2 (ja) 1988-09-27 1988-09-27 半導体装置

Publications (2)

Publication Number Publication Date
DE68911815D1 true DE68911815D1 (de) 1994-02-10
DE68911815T2 DE68911815T2 (de) 1994-06-09

Family

ID=17075265

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68911815T Expired - Fee Related DE68911815T2 (de) 1988-09-27 1989-07-19 Halbleiteranordnung mit verbesserter Elementisolierungsfläche.

Country Status (4)

Country Link
EP (1) EP0360998B1 (de)
JP (1) JPH0691250B2 (de)
KR (1) KR920009980B1 (de)
DE (1) DE68911815T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3143592B2 (ja) * 1995-09-14 2001-03-07 キヤノン株式会社 表示装置
JP3689505B2 (ja) * 1995-11-01 2005-08-31 キヤノン株式会社 半導体装置の作製方法
JP2019096839A (ja) * 2017-11-28 2019-06-20 ソニーセミコンダクタソリューションズ株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1131675A (en) * 1966-07-11 1968-10-23 Hitachi Ltd Semiconductor device
GB1312299A (en) * 1969-08-04 1973-04-04 Matsushita Electronics Corp Insulated gate semiconductor device
JPS59215742A (ja) * 1983-05-24 1984-12-05 Toshiba Corp 半導体装置

Also Published As

Publication number Publication date
DE68911815T2 (de) 1994-06-09
EP0360998A3 (en) 1990-06-06
EP0360998A2 (de) 1990-04-04
JPH0691250B2 (ja) 1994-11-14
KR920009980B1 (ko) 1992-11-09
JPH0289371A (ja) 1990-03-29
KR900005561A (ko) 1990-04-14
EP0360998B1 (de) 1993-12-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee