GB1312299A - Insulated gate semiconductor device - Google Patents

Insulated gate semiconductor device

Info

Publication number
GB1312299A
GB1312299A GB3588270A GB3588270A GB1312299A GB 1312299 A GB1312299 A GB 1312299A GB 3588270 A GB3588270 A GB 3588270A GB 3588270 A GB3588270 A GB 3588270A GB 1312299 A GB1312299 A GB 1312299A
Authority
GB
United Kingdom
Prior art keywords
region
gate electrode
type
source
stopper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3588270A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP6270869A external-priority patent/JPS4821773B1/ja
Priority claimed from JP6270969A external-priority patent/JPS4821774B1/ja
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Publication of GB1312299A publication Critical patent/GB1312299A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

1312299 Insulated gate field effect transistor MATSUSHITA ELECTRONICS CORP 24 July 1970 [4 Aug 1969(3)] 35882/70 Heading H1K An IGFET includes a region of high impurity concentration, of the same conductivity type as the substrate, acting as an inversion channel stopper, with both ends of the gate electrode extending on an insulating film over the stopper region. In one embodiment a U-shaped source region 2 of n<SP>+</SP> type conductivity is diffused into a p type silicon substrate 1, and an n<SP>+</SP> drain region 3 formed between the limbs of region 2. A p<SP>+</SP> type region 9 is formed at the open end of region 2, and both ends of a gate electrode 5, situated on an insulating film 4, extend to this region. The inversion channel beneath the gate electrode of the device, which is of the "normallyon" type cannot therefore extend around the gate electrode, due to the region 9, and thus leakage from source to drain is prevented. In a second embodiment, the source and drain regions take the form of parallel, longitudinal, regions the gate electrode being situated in parallel between the regions, the stopper region being an annulus surrounding both source and drain regions, both ends of the gate electrode again extending to the stopper region. This embodiment is said to be useful in integrated circuits. In both embodiments a plurality of gate electrodes may be used.
GB3588270A 1969-08-04 1970-07-24 Insulated gate semiconductor device Expired GB1312299A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP6270869A JPS4821773B1 (en) 1969-08-04 1969-08-04
JP6270969A JPS4821774B1 (en) 1969-08-04 1969-08-04
JP6271069 1969-08-04

Publications (1)

Publication Number Publication Date
GB1312299A true GB1312299A (en) 1973-04-04

Family

ID=27297930

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3588270A Expired GB1312299A (en) 1969-08-04 1970-07-24 Insulated gate semiconductor device

Country Status (3)

Country Link
DE (1) DE2038534B2 (en)
FR (1) FR2056969B1 (en)
GB (1) GB1312299A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5192993A (en) * 1988-09-27 1993-03-09 Kabushiki Kaisha Toshiba Semiconductor device having improved element isolation area
JPH0691250B2 (en) * 1988-09-27 1994-11-14 株式会社東芝 Semiconductor device

Also Published As

Publication number Publication date
FR2056969B1 (en) 1977-03-18
FR2056969A1 (en) 1971-05-07
DE2038534A1 (en) 1971-06-24
DE2038534B2 (en) 1973-01-25

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Legal Events

Date Code Title Description
PS Patent sealed
746 Register noted 'licences of right' (sect. 46/1977)
PE20 Patent expired after termination of 20 years