GB1131675A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
GB1131675A
GB1131675A GB3014467A GB3014467A GB1131675A GB 1131675 A GB1131675 A GB 1131675A GB 3014467 A GB3014467 A GB 3014467A GB 3014467 A GB3014467 A GB 3014467A GB 1131675 A GB1131675 A GB 1131675A
Authority
GB
United Kingdom
Prior art keywords
semi
conductor
prevented
conductors
igfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3014467A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB1131675A publication Critical patent/GB1131675A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

1,131,675. Semi-conductor devices. HITACHI Ltd. 29 June, 1967 [11 July, 1966], No. 30144/67. Heading H1K. Regions of enhanced conductivity are provided at the surface of a semi-conductor body to prevent current passing between separated devices by an inversion layer which would otherwise be formed under metallic tracks running across the passivation. As shown in Fig. 3 a NOT unit is formed by a P-channel enhancement mode IGFET 12a, 14b, 13a the maximum gate potential of which is clamped to the breakdown voltage of a diode 16a, 11a. Parasitic IGFET action (16a, 17b, 12a) is prevented by the provision of a N<SP>+</SP> region 11b. Particularly if the extent beneath the surface conductors of the highly doped region is large, sharp capacitance variations between conductors and the semi-conductor substrate are also prevented. Reference has been directed by the Comptroller to Specifications 1,059,739 and 1,051,720.
GB3014467A 1966-07-11 1967-06-29 Semiconductor device Expired GB1131675A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4480466 1966-07-11

Publications (1)

Publication Number Publication Date
GB1131675A true GB1131675A (en) 1968-10-23

Family

ID=12701595

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3014467A Expired GB1131675A (en) 1966-07-11 1967-06-29 Semiconductor device

Country Status (2)

Country Link
DE (1) DE1589891B (en)
GB (1) GB1131675A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2029058A1 (en) * 1969-06-26 1971-01-07 N V Philips Gloeilampenfabne ken, Eindhoven (Niederlande) Semiconductor arrangement with a field effect transistor with an isolated gate electrode
DE2044027A1 (en) * 1969-09-05 1971-03-25 Hitachi Ltd Semiconductor arrangement for suppressing the formation of interference MOSFETs in integrated circuits
FR2063062A1 (en) * 1969-09-29 1971-07-02 Sony Corp
US3649885A (en) * 1969-07-03 1972-03-14 Philips Corp Tetrode mosfet with gate safety diode within island zone
FR2323232A1 (en) * 1975-09-08 1977-04-01 Siemens Ag MOUNTING TO PROTECT INPUTS OF INTEGRATED MOS CIRCUITS
EP0072690A2 (en) * 1981-08-17 1983-02-23 Fujitsu Limited A MIS device and a method of manufacturing it
EP0360998A2 (en) * 1988-09-27 1990-04-04 Kabushiki Kaisha Toshiba Semiconductor device having improved element isolation area
EP0515833A1 (en) * 1991-05-02 1992-12-02 Nec Corporation Semiconductor integrated circuit device having wells biased with different voltage levels
US5192993A (en) * 1988-09-27 1993-03-09 Kabushiki Kaisha Toshiba Semiconductor device having improved element isolation area

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2029058A1 (en) * 1969-06-26 1971-01-07 N V Philips Gloeilampenfabne ken, Eindhoven (Niederlande) Semiconductor arrangement with a field effect transistor with an isolated gate electrode
FR2047958A1 (en) * 1969-06-26 1971-03-19 Philips Nv
US3649885A (en) * 1969-07-03 1972-03-14 Philips Corp Tetrode mosfet with gate safety diode within island zone
DE2044027A1 (en) * 1969-09-05 1971-03-25 Hitachi Ltd Semiconductor arrangement for suppressing the formation of interference MOSFETs in integrated circuits
FR2068743A1 (en) * 1969-09-05 1971-09-03 Hitachi Ltd
FR2063062A1 (en) * 1969-09-29 1971-07-02 Sony Corp
FR2323232A1 (en) * 1975-09-08 1977-04-01 Siemens Ag MOUNTING TO PROTECT INPUTS OF INTEGRATED MOS CIRCUITS
EP0072690A2 (en) * 1981-08-17 1983-02-23 Fujitsu Limited A MIS device and a method of manufacturing it
EP0072690A3 (en) * 1981-08-17 1983-11-09 Fujitsu Limited A mis device and a method of manufacturing it
EP0360998A2 (en) * 1988-09-27 1990-04-04 Kabushiki Kaisha Toshiba Semiconductor device having improved element isolation area
EP0360998A3 (en) * 1988-09-27 1990-06-06 Kabushiki Kaisha Toshiba Semiconductor device having improved element isolation area
US5192993A (en) * 1988-09-27 1993-03-09 Kabushiki Kaisha Toshiba Semiconductor device having improved element isolation area
EP0515833A1 (en) * 1991-05-02 1992-12-02 Nec Corporation Semiconductor integrated circuit device having wells biased with different voltage levels

Also Published As

Publication number Publication date
DE1589891B (en) 1970-11-26

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