DE2029058A1 - Semiconductor arrangement with a field effect transistor with an isolated gate electrode - Google Patents

Description

"Semiconductor arrangement with a field effect transistor insulated gate electrode ".

The invention relates to a semiconductor device with a field effect transistor with an insulated gate electrode, a semiconductor body having a substrate region from one Contains conductivity type, the two in the semiconductor body surrounds separate zones of the other conductivity type bordering the surface of the substrate area, which zones together with a channel area lying between them on the surface: Ides substrate area form an uninterrupted surface area, on the surface of which an insulating layer is applied, on which a gate electrode extends which is at least partially above the channel region, and wherein the insulating layer exerts a sufficient effect on the adjacent surface layer of the substrate area.

0Q9882 / H53

It is known that undesired channel formation often occurs on the surface of such semiconductor arrangements, especially at points under the gate electrode or under its Zmleitleiter, insofar as this is on the Insulating layer extends and, for example, different circuit elements integrated in a semiconductor body with one another connects. As a result, unwanted electrical Connections are formed between various circuit elements, thereby reducing the effect of the circuit is affected.

For the sake of clarity, it should also be noted that the field effect transistors mentioned above are usually of the enhancement type in which channel formation only occurs under the influence of the potential differences applied during operation, channels being formed by inversion on the surface. In this context, under "is undesirable Channel formation "to understand that channel formation in the outside of the area in which the of the gate electrode controlled current flows between the source and the sink, inversion creates disturbing leakage paths.

It has already been proposed in such semiconductor arrangements locally under the conductor tracks interconnecting the various circuit elements, surface zones in the Apply substrate area that has the same conductivity type as the substrate area and a higher doping concentration than have this substrate area. This eliminates unwanted surface channels that are located under the conductor

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can easily form tracks in the substrate area, interrupted at the location of the surface zones mentioned.

Because of the need for these more highly doped surface zones Space, however, the circuit elements must be attached at a relatively large mutual distance whereby the circuit as a whole takes up a relatively large surface area. Furthermore has found out that disturbing channel formation can also occur in places that are not under a conductor track, whereby the solution described with more highly doped zones under the conductor tracks is not always satisfactory.

In another known solution, the field effect transistors are completely separated from one another at a certain distance lying higher doped zone surrounded. In this way, the outside of the under the conductor tracks are also Areas occurring surface channels interrupted, so that the formation of uncontrolled leakage paths between the semiconductor zones of the various circuit elements is practical is completely avoided. However, it is evident that with this solution the number of circuit elements per surface unit is further reduced compared to the method described above.

The invention aims to provide a particularly simple solution to create to inhibit undesired channel formation, in which the mentioned disadvantages of the known method described completely or at least to a considerable extent avoided will.

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ORIGINAL INSPECTED

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The invention is based, inter alia, on the knowledge that it is desirable for a good transistor effect that a high-resistance substrate is used in which easily surface channels can be formed. In this case, the breakdown voltage between the zones of the source and the Sink and the substrate are usually higher than with consideration of the electrical occurring during operation of the arrangement Potential differences is required.

Furthermore, the invention is based on the knowledge that the fact that the breakdown voltage mentioned is the required Value can be used to counteract undesired channel formation in an appropriate manner, so that practically no additional space is taken up on the surface of the substrate.

The semiconductor device of the type mentioned in the introduction is characterized according to the invention in that the uninterrupted surface area on the surface is surrounded by a zone belonging to the substrate area of one conductivity type, said zone being connected to at least one of the two mentioned zones of the field effect transistor and a higher doping concentration than the channel region and that part of the substrate area adjoining the mentioned zone.

This way there is an unwanted channeling counteracted by the fact that the substrate area is made locally lower, whereby the fact that the Breakdown voltage between the electrode zones and the

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Substrate generally exceeds the required value, by taking advantage of "that it is ensured that the more highly doped substrate zone, where necessary, adjoins the electrode zone. The expert can determine in the usual way how high the doping of the substrate zone can be selected without affecting the breakdown voltage of the electrode zones assumes a value that is too low, while on the other hand the undesired channel formation is nevertheless expedient, is inhibited.

By using this more highly doped surface zone, the threshold voltage for parasitic channel formation, i.e. canal formation outside the actual canal area of the transistor increased. If necessary, e.g. for Increase in the threshold voltage of the transistor also the Doterung concentration in the canal area can be increased, as long as the latter concentration is lower than that of the The surface zone mentioned is not as light in this surface zone as in the canal area due to inversion Channel formation occur. For a satisfactory protection it is only necessary that the threshold value voltage difference between the canal area and the Oberfläohönaone in such a way it is great that, with the potential differences occurring in the operating state, none outside the canal area Channel formation occurs.

Besides the fact that the solution according to the invention to the problem of undesired channel formation is simple Way to realize it, it is important that this

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Solution results in a particularly great natural stability, so that higher temperatures and a long operating time of the integrated circuit - at least with regard to the undesired channel formation - practically do not impair the effect of the arrangement. This natural stability is due to the fact that channeling with the help of
doped semiconductor regions is prevented. For example, the conductivity of the surface of the substrate area could also be incorporated into the insulating layer on the surface
built-in electrical charges are influenced. Without taking into account the fact that such insulating layers with built-in charges are difficult to reproduce
Can be produced in a way that these built-in charges can easily shift under the influence of electric fields even with a relatively small increase in temperature. In contrast, conventional semiconductor doping is practically immobile up to considerably higher temperatures.

The invention is of particular importance for integrated semiconductor arrangements with a field effect transistor
insulated gate electrode and at least one other
Circuit element, wherein at least one third zone of the other conductivity type is attached in the substrate area,
which belongs to the further circuit element. Such an integrated semiconductor arrangement is characterized according to the invention in that the zone belonging to the substrate region of one conductivity type is connected to at least one of the
two mentioned zones of the field effect transistor as well
adjoins the third zone.

009882 / UB3

ORIGINAL INSPECTED

Such integrated semiconductor arrangements have the essential advantage that the channel interrupting Substrate zone practically does not take up any additional space, thereby reducing the number of circuit elements per surface unit can be relatively large

The further circuit element is preferably likewise a field effect transistor with an insulated gate electrode with two separate zones of the other conductivity type and a channel area in between. It should be evident that the invention also when using field effect transistors with more than one insulated gate electrode, such as a tetrode field effect transistor, matters. A semiconductor arrangement with such a transistor is characterized in that that the channel region of the field effect transistor from at least consists of two parts, these two parts by a further zone belonging to the field effect transistor different conductivity type are separated from each other and a gate electrode is located above each of these parts. Such a field effect transistor with several isolated Gate electrodes can also be viewed as a series connection of two or more field effect transistors each have a gate electrode, the other zone of the other conductivity type and the sink of the one transistor as well as the source of the next Transistor forms. It may be necessary for different applications that the further zone from

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ORIGINAL INSPECTED

Provide a connection wire for the other conductivity type is.

A special embodiment of the semiconductor arrangement according to the invention is characterized in that the zone of one conductivity type on all sides to the uninterrupted surface area of the field effect transistor adjoins. Preferably the zone is of one conductivity type the entire surface of the substrate area, this zone at least one opening on the surface has, the size of which is equal to the uninterrupted surface area of the field effect transistor and which is occupied by this field effect transistor.

In this way, particularly stable semiconductor arrangements are obtained in which - with the exception of the channel region of the field effect transistor - the entire surface of the substrate is protected from channeling. Furthermore, the completely adjacent enclosure of the uninterrupted surface area of the field effect transistor is essential The advantage that the size of the channel area is precisely defined, which means that edge effects can be avoided. The channel area can be limited to a part of the area covered by the gate electrode, with the field lines run practically completely parallel between the zones of the source and the sink. Especially with field effect transistors with a relatively short channel length is through the Prevention of the occurrence of edge effects, the presence of which at the edges of the canal area causes the field

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Lines no longer run straight and parallel, an improvement the electrical properties of the field effect transistor obtain.

The completely adjacent enclosure mentioned is
This is particularly important in the case of field effect transistors with several gate electrodes.

In a further particular embodiment of the semiconductor arrangement according to the invention, the surface doping concentration of the zone of one conductivity type is lower than that of the adjacent zones of the other
Conductivity type.

In this way, the breakdown voltage between the electrode zones of the field effect transistor and the substrate area is essentially determined by the doping concentration of the substrate zone, so that the doping of the electrode zones is fully adapted to the desired properties, in particular to the desired low series resistance
can be.

In a further preferred embodiment, the zone of one conductivity type extends in a direction transverse to the surface from this surface over the
adjacent zone (s) of the other conductivity type and in a direction parallel to the surface to below said adjacent zone (s). Preferably is
the zone of the other conductivity type for the most part in
embedded the zone of one conductivity type.

During manufacture, this structure has the advantage that

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the alignment of the masks for the attachment of windows in a masking layer is not particularly large Accuracy needs to be done. Thanks to mutual The overlap of the substrate zone and the electrode zones is completely adjacent even in the case of an imprecise alignment Enclosure secured.

Furthermore, this structure is due to the aforementioned Overlap the capacitance between the electrode zones and the substrate area can be relatively large, which is often in connection with the occurrence of interference voltages is advantageous and as a result of which a more favorable electrical behavior is obtained at higher temperatures, e.g. is in many circuits the sink of a first field effect transistor with the gate electrode of a second field effect transistor tied together. If an interference voltage now appears at the drain of the second transistor, it is over the generally low capacitance between the drain and the gate electrode of this transistor also forms the gate electrode reach. In the present case, there is a voltage division due to the series connection of the mentioned * Capacitance between the drain and the gate electrode and the capacitance between the drain of the first transistor and the Substrate area. Depending on the capacity of the latter, only a smaller part of the interference voltage is applied to the Gate electrode appear. This reduced susceptibility to failure is important e.g. in the case of logical circuits, in field effect transistors with a low threshold

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value voltage can be applied.

In a further embodiment of the semiconductor arrangement According to the invention, the insulating layer lying on the surface has a thick and a thin part, wherein the part of the insulating layer lying above the channel region belongs to the thin part of this layer.

In this way, higher breakdown voltages can be achieved between the electrode zones and the substrate area will. Outside the channel regions, the channel formation is now due to the greater thickness of the insulating layer as well as also inhibited by the presence of the more highly doped substrate zone. This can reduce the doping concentration of the Substrate zone can be selected to be lower, so that the electrode zones can have a higher breakdown voltage.

The invention also relates to a method for producing semiconductor arrangements with a field effect transistor with an insulated gate electrode, which is characterized in that a substrate area of one Conductivity of a semiconductor body on a surface with a zone of a conductivity type with a higher doping concentration than the adjacent part of the substrate area is provided, which zone is a Has opening, and that local impurities are applied in the substrate area via at least two windows in a mask, so that two separate zones from formed another conductivity type of the field effect transistor and a canal area lying between these zones

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ORIGINAL INSPECTED

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is obtained, the channel area lying entirely in the opening to be made in the first-mentioned machining and this opening is also at most the same size as the uninterrupted surface area of the field effect transistor Has.

It should be noted that the zone of one conductivity type can be applied if the zones of the other conductivity type are already present in the semiconductor body. Preferably, however, the order of the rows is chosen in reverse and the zones of the other conductivity type are attached, after the one conductivity type zone is obtained.

The method according to the invention has the advantage that it can be carried out in a simple manner without a precise alignment of masks the field effect transistor is completely surrounded by the zone of one conductivity type, that the parts of the surface over the impurities of one or the other conductivity type in the semiconductor body be attached, overlap.

Preferably the surface concentrations are on Impurities chosen such that the parts of the semiconductor body that contain the two types of impurities included, to the electrode zones of the field effect transistor belong.

A further embodiment of the method according to the invention is therefore characterized in that in the Formation of the zones of the other conductivity type impurities in the semiconductor body up to a

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■ ORIGINAL! MSPECTEi:

-13-: ..: ■■■■■: ■: ■■ '. ■ y '.' .. /

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Attenuation concentration of the zone of the concentration exceeding one conductivity type can be applied.

Some embodiments of the invention are shown in FIG Drawing shown and are described in more detail below. Show it:

1 shows a circuit diagram of an arrangement with a field effect transistor with insulated gate electrode;

Fig. 2 schematically a part of a plan view of a Semiconductor device according to the invention, which the circuit contains according to Fig. T in integrated form; and

3 schematically shows a cross section through this arrangement along the line III-III of FIG. 2;

FIG. H schematically shows a cross section through part of a further embodiment of the semiconductor arrangement according to the invention; FIG.

Fig. 5 schematically a part of a plan view of a third embodiment of the semiconductor device according to Invention, and

6 schematically shows a cross section through this arrangement along the line VI-VI in FIG. 5.

The invention can be applied both to field effect transistors as well as in integrated circuits with one or more field effect transistors. For example, a integrated design of a known circuit with field effect transistors described, of which in Fig. 1 the circuit diagram is shown. This circuit can be used, for example, as a storage element in a shift register that consists of

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ORIGINAL. 5NSPECTED

a circuit unit consisting of some of these elements can be built. The memory element contains six field effect transistors with an insulated gate electrode

T ₁ to IV, of which the transistors T ₀ and T ^ - as Be-Io 3 ο

load impedances are switched. For this purpose, the Gate electrodes of these transistors T "and T" with the respective Sinks connected. The storage element is using controlled by four clock pulses 0 .. to 0., whereby the dem Information supplied to input 10 to output TT of the Storage element can be pushed away.

Since the effect of the circuit is not essential for the invention, it will not be discussed in more detail. It is important that the transistors T ₁ to TV must be well insulated from one another and that when they are integrated in a semiconductor body, no undesired electrical connections should occur as a result of channel formation.

Figures 2 and 3 show how the circuit of FIG e.g. could be integrated in a semiconductor body.

The semiconductor arrangement according to Figures 2 and 3 contains a field effect transistor T ₁ , T_, T "with insulated gate electrode 10, 0 and 0 .., wherein in a substrate area of one conductivity type of a semiconductor body 21 a number of separated and attached to the surface 22 of the substrate area 20 bordering zones 12, I3 and Ik of the other conductivity type are attached, which zones 12, 13 and together with the channel region 23, 26, 27 lying between these zones on the surface 22 of the substrate region 20 form a contiguous, uninterrupted surface area, with on the surface 22 is an insulating layer 2k ,

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ORIGINAL INSPECTED

on which the gate electrodes 10, 0 'and 0 ₂ extend, which are at least partially above the channel region 23, 26, 27.

According to the invention, the uninterrupted surface area on the surface 22 is surrounded by a zone 25 of one conductivity type belonging to the substrate area 20, this zone 25 being connected to at least one of the mentioned zones 12, 13 and I ^ of the field effect transistor T ₁ , T ₃ , T ₃ and has a higher doping concentration than that part of the substrate region 20 which borders on this zone 25. Silicon dioxide, for example, can be used as the insulating layer. Since a certain positive charge, for example in the form of sodium ions, is practically always introduced into such a layer, the insulating layer will attract the majority charge carriers on the surface of the substrate area under the insulating layer when using n-conducting semiconductor material. Since this enriched layer is present both outside the channel region and in the channel region, this enriched layer does not protect against undesired channel formation, but it does influence the threshold voltage of the transistor. Protection against undesired channel formation requires the application of a zone around the transistor, the doping concentration of this zone being greater than that of the channel region.

The transistor T ₁ , T ₂ , T_, whose sink 12 also acts as a source, forms a ring circuit of three field effect

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ORIGINAL! MSPECTED

transistors with three electrode zones 12, 13 and I **, whereby the sink of a transistor always forms the source of the subsequent transistor of the ring circuit, while three channel regions 23, 2.6 and 27 separated from one another by zones 12, 13 and 1Ί are provided, above
each of which a gate electrode 10, 0 ″ or jZL extends.

In the semiconductor device according to the invention, is preferred at least one further circuit element, e.g. one connected to the gate electrode of the field effect transistor Protection diode, integrated. In the present embodiment, for example, there is a second ring circuit of three field effect transistors Tl, T_ and T ^ in the same semiconductor body attached, wherein in the substrate area at least a third zone, e.g. one of the zones 15 »16, 17» from the other Conductivity type is appropriate, which third zone one Forms part of the further circuit element.

According to the invention, the zone .25 borders on one
Conductivity type also to the third zone 15 »16 or 17 ·

In particular in the present example, in which a number of transistors are connected to one another in series, it is important that the series circuit, which is used as a single
Field effect transistor with multiple gate electrodes can be viewed entirely from a zone 25 adjoining the uninterrupted surface area of the series connection
is surrounded by one conductivity type, whereby the different electrode zones 12, 13 and 14 are also outside

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ORIGINAL INSPECTED

of the controlled channel areas "26, 27 and 23 well against each other are isolated. In particular, in the case of transistors arranged in a ring circuit, it is desirable that the the part of the substrate region adjoining the surface of the ring circuit belongs to the more highly doped zone 25.

The sinks 12 and 16 of the transistors T ~ and T ^ are connected to the respective gate electrodes 0- and jZL via windows 18 in the insulating layer Zh. Furthermore, the zone 14, which forms the sink of T ₂ and at the same time the source of T 1, is connected via a window 19 to a connection conductor which at the same time serves as the gate electrode 28 of the transistor T of the second ring circuit. The electrical output of the storage element is the conductor track 11, which is connected to the zone 17 via a window 19 in the insulating layer 2k , while the gate electrode 10 of the transistor T _{1 forms} the electrical input of the element.

The zone 25 of a conductivity type claims the entire surface of the substrate area 20 and has a number, in this case ring-shaped, openings The size of the uninterrupted surface area of the ring-shaped transistors is equal to which openings of these Transistors are ingested.

The invention creates a particularly simple and practical solution for the use of the zone 25 Problem of unwanted channel formation, this solution being entirely through the methods customary in semiconductor technology can be realized. A major benefit of this

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ORfGiNALlNSPECTED

Solution is that the zone 25 takes no or practically no additional space _rs while still providing a complete enclosure of the electrode zones can be achieved, whereby virtually no unwanted channeling may occur more of. It is true that one must be satisfied with a lower breakdown voltage between the electrode zones and the substrate area, but this is entirely harmless for many applications, including many logic circuits.

Furthermore, with the zone 25, a very stable protection against undesired channel formation is obtained because of the usual semiconductor impurities are practically immobile up to relatively high temperatures, in contrast to charges, which are built into the insulating layer and which, in particular, are already present in the presence of electrical voltages a relatively small increase in temperature can move relatively easily. Although the influence of such built-in charges on the conductivity of the part of the substrate adjoining the insulating layer Inhibition of channel formation could be used, is such a * soldering amount because of "the aforementioned relatively large Mobility of the charges as well as the fact that layers with built-in electrical charges are difficult to move can be produced in a reproducible manner, less suitable.

Another embodiment of a field effect transistor, which, for example, instead of the transistor T "according to FIGS. 2 and 3

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OriiGiNAL IfMSPECTi

could be applied, is shown in Fig. 4 in cross section. Corresponding parts are with the same Reference numerals as indicated in FIGS. 2 and 3.

In this embodiment, the zone 29 of one conductivity type extends in a direction transverse to the surface 22 from this surface over the adjoining zones and Ik of the other conductivity type and this zone 29 extends in a direction parallel to the surface 20 to below the adjoining one Zone 1 * 4. The zone 1 * 1 in the substrate region 20 is preferably for the most part - with the exception of the part adjoining the channel region 23 - embedded in the zone 29 of one conductivity type.

Hei this embodiment, is selected in the account of the space required for the most part, the impurity concentration of the zone lower than that of Zone 1 * 4, the capacitance between the electrode zone \ k can and be made large the substrate in a simple manner, while further mutual by a substantial Overlapping of the electrode zones and the zone 29 the production is also simplified. It should be noted that because, in the semiconductor arrangements according to the invention, the zone of one conductivity type adjoins one or more electrode zones, the capacitance between these electrode zones and the substrate is relatively large. The size of this capacitance, which can be increased further in the manner described above, is important in connection with the susceptibility of the circuit to failure. For example, if the Fig. Appear an interference voltage on the electrode zone 15 of the transistor Tr k, this voltage is on the

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ORIGINAL INSPECTED

Capacitance between the zone 15 and the gate electrode 28 also reach the gate electrode 28. As a result, e.g. the transistor Tr, if it is in the non-conductive state, at an undesired point in time due to the aforementioned interference voltage to be made conductive. The interference voltage at the gate electrode 28 forms only part of the interference voltage of the electrode zone 15i because a voltage division across the Series connection of the mentioned, mostly small, capacitance between the zone 15 and the gate electrode 28 and the capacitance takes place between the gate electrode 28 and the substrate area. The latter capacity becomes essentially determined by the capacitance between the substrate and the electrode zone 14 connected to the gate electrode 28. It is evident, therefore, that the sensitivity of the Transistor Tl for interfering signals at its electrode zones becomes smaller as the capacitance between the electrode zone 14 and the substrate region 20 increases.

This embodiment further shows an insulating layer 2k with a thick part 24a and a thin part 24b, the part of the insulating layer lying above the channel region 23 belonging to the thin part 24b. In general, when using such an insulating layer with varying thickness, the doping concentration of zone 29 can be selected to be lower, because a thick insulating layer already inhibits channel formation and increases the favorable influence of the higher doping concentration on the surface of the substrate area. This means that a higher one

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ORIGINAL INSPECTED

Breakdown voltage between the electrode zones and the
Substrate area can be achieved.

The embodiment according to FIGS. 5 and 6 shows a field effect transistor which, for example, could be used instead of T_ in FIGS. In this embodiment, a zone 30 of a conductivity type is applied which extends into the substrate region 20 less deeply than the electrode zones 15 and 17, with the doping of the zone 30
is chosen such that the concentration is greater than the impurity concentration in the electrode zones 15 and 17.

Furthermore, in this embodiment, the channel region 31 is limited to an area that lies completely between two practically parallel, mutually facing sides of the electrode zones 15 and 17 by the zone 30, the delimitation of which in FIG
5 is indicated with a dashed line 32 until it extends between the two electrode zones. In this way edge effects are avoided. In the canal area, which is completely controlled by the gate electrode, the field lines run practically straight and parallel to one another. Field lines that
extend only partially through the area covered by the gate electrode, as can be the case if the channel area is less tightly enclosed
completely avoided, whereby an improvement in the electrical properties is obtained. This improvement is of
of particular importance for field effect transistors with a
relatively low length-to-width ratio of the canal area.

009882 / "1 4-5 3

The invention is particularly important for semiconductor. Orders with an η-conducting substrate area and p-conducting Source and drain electrode zones, because the most commonly used insulating layers have a positive charge and thus an enriching layer on an n-conductive layer Have an effect. By applying special measures, e.g. by using aluminum oxide, but negative charge can also be built into the insulating layer, in in which case a p-type substrate can be used could.

The embodiments described can be completely using methods known in semiconductor technology. For example, from an n-type silicon body with a specific resistance of 8 to TO /L.cm assumed will.

Although the order in which the n and p «* ends end Surface zones are attached, can be chosen as desired, preferably first the n-conducting channel interrupting end Substrate zone attached. The impurities can e.g. by a common diffusion technique, like diffusion from the vapor phase, e.g. with a doped powder as a source, or diffusion from on the semiconductor surface applied doped insulating layers, or be applied by ion bombardment in the semiconductor body.

In a practical method, the substrate area is provided with an η-conductive zone over the entire surface, whose doping concentration is higher than that of the

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Substrate area is and the one or more openings owns. The delimitation of such openings is shown in FIG. 2 with the dashed lines 33 and in FIG. 5 with the dashed lines 32 indicated. E.g. the higher endowed Zone obtained by diffusion of arsenic, being in the

17 zone, for example, a surface concentration of about 1.10 atoms / cm is applied. The η-conductive zone extends e.g., to a depth of about 2 µm in the substrate.

In the after the above-mentioned diffusion processing The closed diffusion mask can then be attached over the window by conventional photo-etching techniques local impurities can be introduced to form the electrode zone of the other conductivity type. By attaching these p-conductive zones, the position of the channel area, which is between the electrode zones, is also determined is set. The windows mentioned are now installed in such a way that at least the entire canal area is covered comes to rest in the opening of an η-conductive zone, while this opening is still filled by the electrode zones will. The windows mentioned can extend above the η-conductive zone. In practice it is such a mutual overlap of the window and the η-conductive zone desirable because it allows the alignment of the mask to obtain the window with a less large Accuracy can be done. In this case, even with a slight displacement of the mask, it is ensured that that the whole opening is occupied by the field effect transistor will.

0098 82 / U S3

Boron, for example, with a surface concentration of about 5 · 10-10 atoms / cm is diffused through the window. The thickness of the electrode zones is, for example, about 2 / µm. This boron concentration is preferably chosen to be higher than the arsenic concentration of the η-conductive zone. In this case, the η-conductive zone takes up very little, namely almost no additional space, so that the greatest possible number of circuit elements can be attached per surface area. Further, the breakdown voltage is then substantially determined by the doping of the η-type region so that the impurity concentration of the electrode zones ψ completely to the required properties, in particular at the required low series resistance, may be adjusted.

In the embodiments according to FIGS. 2, 3 and h , in which the doping of the electrode zones is higher than that of the substrate zone, the openings in the substrate zone are not much larger than the channel area, while furthermore at the contacting points of the electrode zones to avoid a series resistance Transition between the conductor tracks and the electrode zone, openings are also provided in the substrate zone.

The concentrations mentioned by way of example for the substrate and electrode zones can be converted to conventional ones by the person skilled in the art Way to be adapted to the requirements to be made of the semiconductor arrangement to be produced, in particular in relation to the required breakdown voltage of the electrode zones.

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The invention can be used both at ^. 111 *>"- as well as <^ 1OÖ ^ material. Furthermore, the specific resistance of the substrate area can be selected within very wide limits, for example between about 1 Sh .cm and 10 -iL.cm. In particular, Field effect transistors with very low threshold voltages are obtained. The surface concentration of the more highly doped zone belonging to the substrate is preferably between about and selected about 5 x 10 7 atoms / cm,

Finally, the arrangement can be provided with connection conductors in the usual way, e.g. in the form of conductor tracks be, if necessary, the insulating layer on the Place the channel areas can be made thin, after which the assembly is housed in a conventional envelope can be.

It should be clear that the invention is not limited to the embodiments described, but that many variants are possible for the person skilled in the art within the scope of the invention. For example, other semiconductor materials such as

III V
Germanium and A -B compounds are used. Aluminum oxide, silicon nitride or a layer consisting partly of silicon oxide and partly of silicon nitride, for example, can also be used as the insulating layer. When applying an insulating layer with one thick and one

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thin part is the thickness of the thin part e.g. O, OBbis. 0.3 / van, while the thickness of the remaining part is, for example, 0.5 to 2 / mn. The connecting conductors can consist of aluminum, another highly conductive material or a combination of such materials. All customary impurities are suitable as dating agents, whereby these are preferably chosen when using diffusion processes that the diffusion coefficient of the η-conductive Impurity is considerably smaller than that of the p-conducting impurity, or vice versa, the impurity with the smallest diffusion coefficient being applied first in the semiconductor body. When choosing the row order in which the diffusion processes are carried out, a difference in the precipitation coefficient of the impurities to be used at the interface between the semiconductor and the insulating layer can also play a role.

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Claims (1)

Patent claims : 1 * semiconductor device with a field effect transistor insulated door electrode, wherein a semiconductor body contains a substrate region of a conductivity type which is in the Semiconductor body two zones separated from one another and adjoining the surface of the substrate region from the other Conductivity type includes which zones together with an intermediate canal area on the surface of the Subetratgebietes an uninterrupted surface area form, wherein on the surface is an insulating layer on which a gate electrode extends at least partially above the channel area, and wherein the insulating layer on the adjacent surface layer of the Substrate area exerts an enriching effect, thereby marked that the uninterrupted surface area is surrounded on the surface by a zone belonging to the substrate area of one conductivity type, the mentioned zone to at least one of the two mentioned zones of the field effect transistor and a higher doping concentration than the channel region and the mentioned Zone bordering part of the substrate area. 2 «semiconductor device according to claim 1, in which at least a further circuit element is integrated, wherein in the substrate area at least one third zone of the other conductivity type is attached, which forms part of the further circuit element, characterized in that the to the Zone of one conductivity type belonging to the substrate area G09882 / U53 also borders the third zone. 3 · Semiconductor arrangement according to claim 1 or 2, characterized characterized in that the channel region of the field effect transistor consists of two parts, these parts being replaced by another Zone belonging to the field effect transistor from the other conduction Ability type are separated from each other, while a gate electrode is located above each of these parts. 4. Semiconductor arrangement according to claim 3, characterized in that -the further zone of the other conductivity type with a connection conductor is provided. 5. Semiconductor arrangement according to claim 2 or claim 2 and one of claims 3 and k, characterized in that the further circuit element is also a field effect transistor with an insulated gate electrode with two separate zones of the other conductivity type and an intermediate channel region. 6. Semiconductor arrangement according to one or more of the preceding claims, characterized in that the zone of one conductivity type completely encloses the uninterrupted surface area. 7. Semiconductor arrangement according to claim 6, characterized in that that the zone of one conductivity type covers the whole surface of the substrate area claimed, this zone having at least one opening, the size of which is equal to the uninterrupted surface area of the field effect transistor and which is occupied by this transistor. 009882 / U53 8. Semiconductor arrangement according to one or more of the standing claims: characterized in that the surface concentration the doping of the zone of one conductivity type is lower than that of the doping of the adjacent Zone (s) is of the other conductivity type. 9 · Semiconductor arrangement according to claim 8, characterized in that the zone of one conductivity type is in. a direction transverse to the surface from this surface across the adjacent zone of the other conductivity type extends across the substrate area and in one to the surface parallel direction to below this adjacent Zone is enough. 10. Semiconductor arrangement according to claim 9 »characterized in that that the zone of the other conductivity type in Substrate area largely in the zone of one conductive, type is embedded. · ' 11. Semiconductor arrangement according to one or more of the The preceding claims, characterized in that the insulating layer lying on the surface one thick and one having thin part, the one above the channel area lying part of the insulating layer belongs to the thin part of this layer. 12. Semiconductor arrangement according to one or more of the The preceding claims, characterized in that the substrate area is η-conductive and the zones of the other conductivity type be p-type. 009882/1453 13. Semiconductor arrangement according to claim 12, characterized characterized in that the insulating layer is at least partially consists of silicon dioxide. 1 ^. Method for producing a semiconductor arrangement according to one or more of the preceding claims, characterized in that a substrate region of one conductivity type in a semiconductor body is provided on one surface with a zone of one conductivity type which has a higher doping concentration than the adjoining part of the substrate region and which has an opening, and that local impurities in the substrate area are applied via at least two windows in a mask to form the separate zones of the other conductivity type of the field effect transistor and to maintain a channel area located between these zones, the channel area being completely in the same as the former mentioned processing is to be attached opening and this opening also has at most the same size as the uninterrupted surface area of the field effect transistor. Method according to claim 1, characterized in that, during the formation of the zones of the other conductivity type, impurities are applied in the semiconductor body, specifically up to a concentration which is higher than the impurity concentration of the zone of one conductivity type. 16. The method according to claim \ h or 15, characterized in that the zones of the other conductivity type are applied after the zone of one conductivity type has been obtained. 009882/1453 " ORIGINAL INSPECTED Empty soap