DE68907295D1 - Verfahren zum herstellen einer supraleitenden duennschicht vom wismut-typ. - Google Patents

Verfahren zum herstellen einer supraleitenden duennschicht vom wismut-typ.

Info

Publication number
DE68907295D1
DE68907295D1 DE8989402352T DE68907295T DE68907295D1 DE 68907295 D1 DE68907295 D1 DE 68907295D1 DE 8989402352 T DE8989402352 T DE 8989402352T DE 68907295 T DE68907295 T DE 68907295T DE 68907295 D1 DE68907295 D1 DE 68907295D1
Authority
DE
Germany
Prior art keywords
wismut
super
producing
type
thick layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8989402352T
Other languages
English (en)
Other versions
DE68907295T2 (de
Inventor
Kenjiro C O Itami Works Higaki
Keizo C O Itami Works Harada
Naoji C O Itami Works Fujimori
Hideo C O Itami Works Itozaki
Shuji C O Itami Works Yazu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Publication of DE68907295D1 publication Critical patent/DE68907295D1/de
Application granted granted Critical
Publication of DE68907295T2 publication Critical patent/DE68907295T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0296—Processes for depositing or forming copper oxide superconductor layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0296—Processes for depositing or forming copper oxide superconductor layers
    • H10N60/0576—Processes for depositing or forming copper oxide superconductor layers characterised by the substrate
    • H10N60/0604—Monocrystalline substrates, e.g. epitaxial growth
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/725—Process of making or treating high tc, above 30 k, superconducting shaped material, article, or device
    • Y10S505/73—Vacuum treating or coating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/725—Process of making or treating high tc, above 30 k, superconducting shaped material, article, or device
    • Y10S505/73—Vacuum treating or coating
    • Y10S505/731—Sputter coating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/725—Process of making or treating high tc, above 30 k, superconducting shaped material, article, or device
    • Y10S505/73—Vacuum treating or coating
    • Y10S505/732—Evaporative coating with superconducting material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/725—Process of making or treating high tc, above 30 k, superconducting shaped material, article, or device
    • Y10S505/742—Annealing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/775—High tc, above 30 k, superconducting material
    • Y10S505/776—Containing transition metal oxide with rare earth or alkaline earth
    • Y10S505/782—Bismuth-, e.g. BiCaSrCuO

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Compounds Of Heavy Metals (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)
  • Physical Vapour Deposition (AREA)
DE89402352T 1988-08-29 1989-08-29 Verfahren zum Herstellen einer supraleitenden Dünnschicht vom Wismut-Typ. Expired - Fee Related DE68907295T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63214130A JP2664070B2 (ja) 1988-08-29 1988-08-29 複合酸化物超電導薄膜の作製方法

Publications (2)

Publication Number Publication Date
DE68907295D1 true DE68907295D1 (de) 1993-07-29
DE68907295T2 DE68907295T2 (de) 1993-11-25

Family

ID=16650722

Family Applications (1)

Application Number Title Priority Date Filing Date
DE89402352T Expired - Fee Related DE68907295T2 (de) 1988-08-29 1989-08-29 Verfahren zum Herstellen einer supraleitenden Dünnschicht vom Wismut-Typ.

Country Status (8)

Country Link
US (1) US5051398A (de)
EP (1) EP0357500B1 (de)
JP (1) JP2664070B2 (de)
KR (1) KR900004047A (de)
CN (1) CN1018311B (de)
AU (1) AU615102B2 (de)
CA (1) CA1337719C (de)
DE (1) DE68907295T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE68921138T3 (de) * 1988-10-03 1998-07-16 Sumitomo Electric Industries Verfahren zur Herstellung eines Oxidverbindungssupraleiters des Bi-Sr-Ca-Cu-Systems.
CA2037481C (en) * 1990-03-08 1998-11-10 Noriki Hayashi Method of preparing oxide superconducting film
EP0643400B1 (de) * 1991-06-04 1998-01-21 Matsushita Electric Industrial Co., Ltd. Herstellungsverfahren für Dünnschicht-Supraleiter
US7617474B2 (en) * 1997-09-17 2009-11-10 Synopsys, Inc. System and method for providing defect printability analysis of photolithographic masks with job-based automation
JP4172040B2 (ja) * 2004-03-23 2008-10-29 独立行政法人科学技術振興機構 固相フラックスエピタキシー成長法
CN113322514A (zh) * 2021-05-24 2021-08-31 沈阳大学 分子束外延技术制备(00l)择优取向低熔点铋薄膜的方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0772349B2 (ja) * 1987-05-12 1995-08-02 住友電気工業株式会社 大面積化合物薄膜の作製方法および装置
ATE115104T1 (de) * 1988-02-05 1994-12-15 Hoechst Ag Supraleiter und verfahren zu seiner herstellung.
US4880771A (en) * 1988-02-12 1989-11-14 American Telephone And Telegraph Company, At&T Bell Laboratories Bismuth-lead-strontium-calcium-cuprate superconductors
JPH0286014A (ja) * 1988-06-17 1990-03-27 Sumitomo Electric Ind Ltd 複合酸化物超電導薄膜と、その成膜方法

Also Published As

Publication number Publication date
CN1041237A (zh) 1990-04-11
US5051398A (en) 1991-09-24
KR900004047A (ko) 1990-03-27
CA1337719C (en) 1995-12-12
JPH0264021A (ja) 1990-03-05
CN1018311B (zh) 1992-09-16
AU615102B2 (en) 1991-09-19
AU4086189A (en) 1990-03-01
DE68907295T2 (de) 1993-11-25
EP0357500B1 (de) 1993-06-23
EP0357500A1 (de) 1990-03-07
JP2664070B2 (ja) 1997-10-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee