DE60318795D1 - Prüfung von integrierten Schaltungen - Google Patents

Prüfung von integrierten Schaltungen

Info

Publication number
DE60318795D1
DE60318795D1 DE60318795T DE60318795T DE60318795D1 DE 60318795 D1 DE60318795 D1 DE 60318795D1 DE 60318795 T DE60318795 T DE 60318795T DE 60318795 T DE60318795 T DE 60318795T DE 60318795 D1 DE60318795 D1 DE 60318795D1
Authority
DE
Germany
Prior art keywords
testing
integrated circuits
circuits
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60318795T
Other languages
English (en)
Other versions
DE60318795T2 (de
Inventor
Susan Stirrat
Kang Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of DE60318795D1 publication Critical patent/DE60318795D1/de
Application granted granted Critical
Publication of DE60318795T2 publication Critical patent/DE60318795T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G01R31/31835—Analysis of test coverage or failure detectability
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2894—Aspects of quality control [QC]
DE60318795T 2002-09-26 2003-09-24 Prüfung von integrierten Schaltungen Expired - Lifetime DE60318795T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/255,480 US6907378B2 (en) 2002-09-26 2002-09-26 Empirical data based test optimization method
US255480 2002-09-26

Publications (2)

Publication Number Publication Date
DE60318795D1 true DE60318795D1 (de) 2008-03-13
DE60318795T2 DE60318795T2 (de) 2009-02-05

Family

ID=31977848

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60318795T Expired - Lifetime DE60318795T2 (de) 2002-09-26 2003-09-24 Prüfung von integrierten Schaltungen

Country Status (5)

Country Link
US (1) US6907378B2 (de)
EP (1) EP1403651B1 (de)
JP (1) JP2004119963A (de)
DE (1) DE60318795T2 (de)
SG (1) SG123560A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7596731B1 (en) * 2006-04-07 2009-09-29 Marvell International Ltd. Test time reduction algorithm
US7532024B2 (en) 2006-07-05 2009-05-12 Optimaltest Ltd. Methods and systems for semiconductor testing using reference dice
US9874870B2 (en) * 2009-08-26 2018-01-23 Fisher-Rosemount Systems, Inc. Methods and apparatus to manage testing of a process control system
US8561021B2 (en) * 2010-02-08 2013-10-15 Microsoft Corporation Test code qualitative evaluation
US8458013B2 (en) 2011-04-12 2013-06-04 Bank Of America Corporation Test portfolio optimization system
US8689066B2 (en) 2011-06-29 2014-04-01 International Business Machines Corporation Integrated circuit test optimization using adaptive test pattern sampling algorithm
US20140281719A1 (en) * 2013-03-13 2014-09-18 International Business Machines Corporation Explaining excluding a test from a test suite
US9418759B2 (en) * 2014-05-06 2016-08-16 Intel IP Corporation Assist circuits for SRAM testing
US10452508B2 (en) 2015-06-15 2019-10-22 International Business Machines Corporation Managing a set of tests based on other test failures
US20170010325A1 (en) * 2015-07-08 2017-01-12 Qualcomm Incorporated Adaptive test time reduction

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0658984A (ja) * 1992-08-11 1994-03-04 Mitsubishi Electric Corp 半導体試験装置
JPH06265596A (ja) * 1993-03-16 1994-09-22 Fujitsu Ltd 多機能デバイス試験方法
JPH10125742A (ja) * 1996-10-22 1998-05-15 Mitsubishi Electric Corp 半導体集積回路の良否判定方法及び半導体集積回路
US6078189A (en) * 1996-12-13 2000-06-20 International Business Machines Corporation Dynamic test reordering
US5771243A (en) * 1997-02-07 1998-06-23 Etron Technology, Inc. Method of identifying redundant test patterns
US5844909A (en) 1997-03-27 1998-12-01 Nec Corporation Test pattern selection method for testing of integrated circuit
KR100299716B1 (ko) * 1997-07-24 2001-09-06 가야시마 고조 Ic시험장치및방법
US6154714A (en) * 1997-11-17 2000-11-28 Heuristic Physics Laboratories Method for using wafer navigation to reduce testing times of integrated circuit wafers
US5983381A (en) * 1997-12-31 1999-11-09 Nec Usa Inc. Partitioning and reordering methods for static test sequence compaction of sequential circuits
JPH11353900A (ja) * 1998-06-11 1999-12-24 Mitsubishi Electric Corp 半導体装置
US7225107B2 (en) * 2001-05-24 2007-05-29 Test Advantage, Inc. Methods and apparatus for data analysis
JP2002237506A (ja) * 2001-02-09 2002-08-23 Mitsubishi Electric Corp 故障解析装置及び故障解析方法、並びに半導体装置の製造方法
AU2002312045A1 (en) * 2001-05-24 2002-12-03 Test Advantage, Inc. Methods and apparatus for semiconductor testing
US6707313B1 (en) * 2003-02-19 2004-03-16 Agilent Technologies, Inc. Systems and methods for testing integrated circuits

Also Published As

Publication number Publication date
US20040061517A1 (en) 2004-04-01
DE60318795T2 (de) 2009-02-05
JP2004119963A (ja) 2004-04-15
SG123560A1 (en) 2006-07-26
EP1403651A3 (de) 2004-07-28
EP1403651A2 (de) 2004-03-31
US6907378B2 (en) 2005-06-14
EP1403651B1 (de) 2008-01-23

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Legal Events

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8364 No opposition during term of opposition