DE60303126D1 - Verfahren und vorrichtung zum sicheren scan-testen - Google Patents

Verfahren und vorrichtung zum sicheren scan-testen

Info

Publication number
DE60303126D1
DE60303126D1 DE60303126T DE60303126T DE60303126D1 DE 60303126 D1 DE60303126 D1 DE 60303126D1 DE 60303126 T DE60303126 T DE 60303126T DE 60303126 T DE60303126 T DE 60303126T DE 60303126 D1 DE60303126 D1 DE 60303126D1
Authority
DE
Germany
Prior art keywords
scan testing
safe scan
safe
testing
scan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60303126T
Other languages
English (en)
Other versions
DE60303126T2 (de
Inventor
Thomas Tkacik
E Spittal
Jonathan Lutz
Lawrence Case
Douglas Hardy
Mark Redman
Gregory Schmidt
Steven Tugenberg
D Fitzsimmons
L Carder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Application granted granted Critical
Publication of DE60303126D1 publication Critical patent/DE60303126D1/de
Publication of DE60303126T2 publication Critical patent/DE60303126T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Storage Device Security (AREA)
DE60303126T 2002-04-30 2003-04-14 Verfahren und vorrichtung zum sicheren scan-testen Expired - Lifetime DE60303126T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US135877 2002-04-30
US10/135,877 US7185249B2 (en) 2002-04-30 2002-04-30 Method and apparatus for secure scan testing
PCT/US2003/011399 WO2004051294A1 (en) 2002-04-30 2003-04-14 Method and apparatus for secure scan testing

Publications (2)

Publication Number Publication Date
DE60303126D1 true DE60303126D1 (de) 2006-03-30
DE60303126T2 DE60303126T2 (de) 2006-07-20

Family

ID=29249555

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60303126T Expired - Lifetime DE60303126T2 (de) 2002-04-30 2003-04-14 Verfahren und vorrichtung zum sicheren scan-testen

Country Status (9)

Country Link
US (2) US7185249B2 (de)
EP (1) EP1499906B1 (de)
JP (1) JP2006505798A (de)
KR (1) KR100966661B1 (de)
CN (1) CN100381834C (de)
AU (1) AU2003224959A1 (de)
DE (1) DE60303126T2 (de)
TW (1) TWI270768B (de)
WO (1) WO2004051294A1 (de)

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Also Published As

Publication number Publication date
EP1499906A1 (de) 2005-01-26
US20030204801A1 (en) 2003-10-30
US7185249B2 (en) 2007-02-27
KR100966661B1 (ko) 2010-06-29
CN100381834C (zh) 2008-04-16
US20070226562A1 (en) 2007-09-27
US7725788B2 (en) 2010-05-25
WO2004051294A1 (en) 2004-06-17
JP2006505798A (ja) 2006-02-16
DE60303126T2 (de) 2006-07-20
CN1650183A (zh) 2005-08-03
AU2003224959A1 (en) 2004-06-23
TW200400431A (en) 2004-01-01
EP1499906B1 (de) 2006-01-04
KR20040104678A (ko) 2004-12-10
TWI270768B (en) 2007-01-11

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