FR2888330B1 - Circuit integre comportant un mode de test securise par detection de l'etat d'un signal de commande - Google Patents
Circuit integre comportant un mode de test securise par detection de l'etat d'un signal de commandeInfo
- Publication number
- FR2888330B1 FR2888330B1 FR0507281A FR0507281A FR2888330B1 FR 2888330 B1 FR2888330 B1 FR 2888330B1 FR 0507281 A FR0507281 A FR 0507281A FR 0507281 A FR0507281 A FR 0507281A FR 2888330 B1 FR2888330 B1 FR 2888330B1
- Authority
- FR
- France
- Prior art keywords
- status
- detecting
- control signal
- integrated circuit
- test mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0507281A FR2888330B1 (fr) | 2005-07-08 | 2005-07-08 | Circuit integre comportant un mode de test securise par detection de l'etat d'un signal de commande |
US11/484,359 US7694197B2 (en) | 2005-07-08 | 2006-07-10 | Integrated circuit comprising a test mode secured by detection of the state of a control signal |
US11/484,355 US7577886B2 (en) | 2005-07-08 | 2006-07-10 | Method for testing an electronic circuit comprising a test mode secured by the use of a signature, and associated electronic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0507281A FR2888330B1 (fr) | 2005-07-08 | 2005-07-08 | Circuit integre comportant un mode de test securise par detection de l'etat d'un signal de commande |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2888330A1 FR2888330A1 (fr) | 2007-01-12 |
FR2888330B1 true FR2888330B1 (fr) | 2007-10-05 |
Family
ID=36123107
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0507281A Expired - Fee Related FR2888330B1 (fr) | 2005-07-08 | 2005-07-08 | Circuit integre comportant un mode de test securise par detection de l'etat d'un signal de commande |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2888330B1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2958063B1 (fr) * | 2010-03-26 | 2012-04-20 | Thales Sa | Dispositif permettant de securiser un bus de type jtag |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1089083A1 (fr) * | 1999-09-03 | 2001-04-04 | Sony Corporation | CIrcuits à semiconducteurs avec circuits de chemin de balayage |
DE10044837C1 (de) * | 2000-09-11 | 2001-09-13 | Infineon Technologies Ag | Schaltungsanordnung und Verfahren zum Detektieren eines unerwünschten Angriffs auf eine integrierte Schaltung |
US7185249B2 (en) * | 2002-04-30 | 2007-02-27 | Freescale Semiconductor, Inc. | Method and apparatus for secure scan testing |
-
2005
- 2005-07-08 FR FR0507281A patent/FR2888330B1/fr not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2888330A1 (fr) | 2007-01-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20090331 |