DE60220736T2 - Herstellungsverfahren für gebondetes Substrat - Google Patents

Herstellungsverfahren für gebondetes Substrat Download PDF

Info

Publication number
DE60220736T2
DE60220736T2 DE60220736T DE60220736T DE60220736T2 DE 60220736 T2 DE60220736 T2 DE 60220736T2 DE 60220736 T DE60220736 T DE 60220736T DE 60220736 T DE60220736 T DE 60220736T DE 60220736 T2 DE60220736 T2 DE 60220736T2
Authority
DE
Germany
Prior art keywords
active
substrates
substrate
layer
composite
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60220736T
Other languages
German (de)
English (en)
Other versions
DE60220736D1 (de
Inventor
Heon Sunnyvale Lee
Chung Ching Saratoga Yang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Publication of DE60220736D1 publication Critical patent/DE60220736D1/de
Application granted granted Critical
Publication of DE60220736T2 publication Critical patent/DE60220736T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Micromachines (AREA)
  • Recrystallisation Techniques (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Element Separation (AREA)
  • Photovoltaic Devices (AREA)
DE60220736T 2001-03-30 2002-04-02 Herstellungsverfahren für gebondetes Substrat Expired - Lifetime DE60220736T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/823,550 US6537846B2 (en) 2001-03-30 2001-03-30 Substrate bonding using a selenidation reaction
US823550 2001-03-30

Publications (2)

Publication Number Publication Date
DE60220736D1 DE60220736D1 (de) 2007-08-02
DE60220736T2 true DE60220736T2 (de) 2008-03-13

Family

ID=25239072

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60220736T Expired - Lifetime DE60220736T2 (de) 2001-03-30 2002-04-02 Herstellungsverfahren für gebondetes Substrat

Country Status (5)

Country Link
US (1) US6537846B2 (https=)
EP (1) EP1246238B1 (https=)
JP (1) JP4198375B2 (https=)
CN (1) CN1286145C (https=)
DE (1) DE60220736T2 (https=)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6362075B1 (en) * 1999-06-30 2002-03-26 Harris Corporation Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide
JP2002305293A (ja) * 2001-04-06 2002-10-18 Canon Inc 半導体部材の製造方法及び半導体装置の製造方法
US6960490B2 (en) * 2002-03-14 2005-11-01 Epitactix Pty Ltd. Method and resulting structure for manufacturing semiconductor substrates
AU2002307578A1 (en) * 2002-04-30 2003-12-02 Agency For Science Technology And Research A method of wafer/substrate bonding
DE602004002888T2 (de) * 2003-05-13 2007-05-31 Becton Dickinson And Co. Vorrichtung und Verfahren zum Sanieren und Entsalzen von biologischen Proben
US7176106B2 (en) * 2003-06-13 2007-02-13 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Wafer bonding using reactive foils for massively parallel micro-electromechanical systems packaging
US7407863B2 (en) 2003-10-07 2008-08-05 Board Of Trustees Of The University Of Illinois Adhesive bonding with low temperature grown amorphous or polycrystalline compound semiconductors
US7026189B2 (en) * 2004-02-11 2006-04-11 Hewlett-Packard Development Company, L.P. Wafer packaging and singulation method
US7422962B2 (en) * 2004-10-27 2008-09-09 Hewlett-Packard Development Company, L.P. Method of singulating electronic devices
FR2888402B1 (fr) * 2005-07-06 2007-12-21 Commissariat Energie Atomique Procede d'assemblage de substrats par depot d'une couche mince de collage d'oxyde ou de nitrure et structure ainsi assemblee
KR100829562B1 (ko) * 2006-08-25 2008-05-14 삼성전자주식회사 기판 접합 구조를 갖는 반도체 레이저 다이오드 및 그제조방법
US20100109115A1 (en) * 2008-11-03 2010-05-06 Ure Michael J Virtual IC wafers and bonding of constitutent IC films
US8748288B2 (en) 2010-02-05 2014-06-10 International Business Machines Corporation Bonded structure with enhanced adhesion strength
EP2654075B1 (de) 2010-03-31 2016-09-28 EV Group E. Thallner GmbH Verfahren zum permanenten Verbinden zweier Metalloberflächen
US9117948B1 (en) 2012-02-02 2015-08-25 The United States Of America As Represented By The Adminstrator Of National Aeronautics And Space Administration Selenium interlayer for high-efficiency multijunction solar cell
WO2017200705A1 (en) * 2016-05-20 2017-11-23 ARES Materials, Inc. Polymer substrate for flexible electronics microfabrication and methods of use
US10736212B2 (en) 2016-05-20 2020-08-04 Ares Materials Inc. Substrates for stretchable electronics and method of manufacture
EP3497714A1 (en) * 2016-08-09 2019-06-19 King Abdullah University Of Science And Technology A semiconductor device including monolithically integrated pmos and nmos transistors
CN107742606B (zh) * 2017-10-30 2024-04-02 桂林电子科技大学 一种键合晶圆的结构及其制备方法
CN110534644B (zh) * 2019-08-30 2021-01-15 华中科技大学 一种双向生长的超晶格相变单元的制备方法及相变存储器

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61182217A (ja) * 1985-02-08 1986-08-14 Toshiba Corp ウエハ接着方法
JPH0472608A (ja) * 1990-05-18 1992-03-06 Toshiba Corp 化合物半導体ウェハの製造方法および製造装置
JP2990036B2 (ja) 1995-02-13 1999-12-13 ティーディーケイ株式会社 光記録媒体およびその製造方法
JPH08316145A (ja) * 1995-05-12 1996-11-29 Fuji Electric Co Ltd 半導体薄膜の成膜方法
US5730852A (en) 1995-09-25 1998-03-24 Davis, Joseph & Negley Preparation of cuxinygazsen (X=0-2, Y=0-2, Z=0-2, N=0-3) precursor films by electrodeposition for fabricating high efficiency solar cells
JP2737748B2 (ja) * 1996-06-21 1998-04-08 日本電気株式会社 化合物半導体の接合方法
FR2751467B1 (fr) * 1996-07-17 1998-10-02 Commissariat Energie Atomique Procede d'assemblage de deux structures et dispositif obtenu par le procede. applications aux microlasers
JP3249408B2 (ja) 1996-10-25 2002-01-21 昭和シェル石油株式会社 薄膜太陽電池の薄膜光吸収層の製造方法及び製造装置
US6036772A (en) 1996-12-30 2000-03-14 Sony Corporation Method for making semiconductor device
US6258620B1 (en) * 1997-10-15 2001-07-10 University Of South Florida Method of manufacturing CIGS photovoltaic devices
US6323417B1 (en) * 1998-09-29 2001-11-27 Lockheed Martin Corporation Method of making I-III-VI semiconductor materials for use in photovoltaic cells
JP2000349266A (ja) * 1999-03-26 2000-12-15 Canon Inc 半導体部材の製造方法、半導体基体の利用方法、半導体部材の製造システム、半導体部材の生産管理方法及び堆積膜形成装置の利用方法
JP4465745B2 (ja) * 1999-07-23 2010-05-19 ソニー株式会社 半導体積層基板，半導体結晶基板および半導体素子ならびにそれらの製造方法

Also Published As

Publication number Publication date
JP4198375B2 (ja) 2008-12-17
US6537846B2 (en) 2003-03-25
DE60220736D1 (de) 2007-08-02
JP2003017375A (ja) 2003-01-17
CN1379436A (zh) 2002-11-13
EP1246238A3 (en) 2003-11-26
CN1286145C (zh) 2006-11-22
EP1246238B1 (en) 2007-06-20
US20030017679A1 (en) 2003-01-23
EP1246238A2 (en) 2002-10-02

Similar Documents

Publication Publication Date Title
DE60220736T2 (de) Herstellungsverfahren für gebondetes Substrat
DE3789172T2 (de) Verfahren zum Montieren eines Silizium-Würfels.
EP0610709B1 (de) Verfahren zur Herstellung einer dreidimensionalen Schaltungsanordnung
DE3879176T2 (de) Oxid-entfernung von metallischen kontaktloechern auf halbleiteranordnungen zum verbessern von hybrid-kaltschweissen.
DE69836707T2 (de) Behandlungsverfahren zum Molekularkleben und Ablösen von zwei Strukturen
EP0703619B1 (de) Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung unter Erreichung hoher Systemausbeuten
DE19842419B4 (de) Verfahren zum Bilden eines Halbleiterelements
DE102011002546B4 (de) Verfahren zum Herstellen einer mehrschichtigen Struktur mit Trimmen nach dem Schleifen
DE102008051494B4 (de) Verfahren zum Herstellen der SOI-Substrate mit einer feinen vergrabenen Isolationsschicht
DE112006000647B4 (de) Verfahren zum Bilden selbst-passivierender Interconnects
DE602006000233T2 (de) Substrat mit einer Metallisierungshaftschicht
US20120115305A1 (en) Method and structure for wafer to wafer bonding in semiconductor packaging
JPH01315159A (ja) 誘電体分離半導体基板とその製造方法
DE102016109166B4 (de) Lötmetallisierungsstapel und Verfahren zum Bilden desselben
EP2381469A1 (en) Filling material and filling method using the same
JPH08505010A (ja) 石英基板上の単結晶シリコン・アイランド作製方法
US11309278B2 (en) Methods for bonding substrates
JP2008521214A (ja) 半導体ウエハの薄型化
DE102014202808A1 (de) Verfahren zum eutektischen Bonden zweier Trägereinrichtungen
DE112004001102B4 (de) Verfahren zur Steuerung der Planheit und der Elektronenbeweglichkeit von mit Diamant beschichtetem Silizium und dadurch gebildeten Strukturen
DE102005052563B4 (de) Halbleiterchip, Halbleiterbauteil und Verfahren zu deren Herstellung
DE102020133890A1 (de) Wafer mit kristallinem silizium und haftstellenreicher polysiliziumschicht
JP2002373931A (ja) ウエハハンドリング方法
CH660176A5 (de) Metall-keramik-verbundelement und verfahren zu dessen herstellung.
EP3140856B1 (de) Verfahren und vorrichtung zum permanenten bonden

Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, US

8328 Change in the person/name/address of the agent

Representative=s name: SCHOPPE, ZIMMERMANN, STOECKELER & ZINKLER, 82049 P

8364 No opposition during term of opposition