DE60218498D1 - Elektronisches gerät - Google Patents

Elektronisches gerät

Info

Publication number
DE60218498D1
DE60218498D1 DE60218498T DE60218498T DE60218498D1 DE 60218498 D1 DE60218498 D1 DE 60218498D1 DE 60218498 T DE60218498 T DE 60218498T DE 60218498 T DE60218498 T DE 60218498T DE 60218498 D1 DE60218498 D1 DE 60218498D1
Authority
DE
Germany
Prior art keywords
test
chain
test interface
electronic device
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60218498T
Other languages
English (en)
Other versions
DE60218498T2 (de
Inventor
Hubertus G Vermeulen
Thomas F Waayers
Guillaume E Lousberg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of DE60218498D1 publication Critical patent/DE60218498D1/de
Application granted granted Critical
Publication of DE60218498T2 publication Critical patent/DE60218498T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318561—Identification of the subpart
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Surgical Instruments (AREA)
  • Valve Device For Special Equipments (AREA)
  • Noodles (AREA)
DE60218498T 2001-09-20 2002-09-04 Elektronisches gerät Expired - Lifetime DE60218498T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP01203565 2001-09-20
EP01203565 2001-09-20
PCT/IB2002/003617 WO2003025595A2 (en) 2001-09-20 2002-09-04 Electronic device

Publications (2)

Publication Number Publication Date
DE60218498D1 true DE60218498D1 (de) 2007-04-12
DE60218498T2 DE60218498T2 (de) 2007-11-08

Family

ID=8180950

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60218498T Expired - Lifetime DE60218498T2 (de) 2001-09-20 2002-09-04 Elektronisches gerät

Country Status (9)

Country Link
US (1) US6988230B2 (de)
EP (1) EP1430319B1 (de)
JP (1) JP4249019B2 (de)
KR (1) KR100896538B1 (de)
CN (1) CN100342241C (de)
AT (1) ATE355534T1 (de)
DE (1) DE60218498T2 (de)
TW (1) TWI232951B (de)
WO (1) WO2003025595A2 (de)

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US7827510B1 (en) 2002-06-07 2010-11-02 Synopsys, Inc. Enhanced hardware debugging with embedded FPGAS in a hardware description language
US7571068B2 (en) * 2002-08-14 2009-08-04 Nxp B.V. Module, electronic device and evaluation tool
US7010722B2 (en) * 2002-09-27 2006-03-07 Texas Instruments Incorporated Embedded symmetric multiprocessor system debug
US7478302B2 (en) * 2003-05-28 2009-01-13 Nxp B.V. Signal integrity self-test architecture
US7246282B2 (en) * 2003-06-25 2007-07-17 Hewlett-Packard Development Company, L.P. Bypassing a device in a scan chain
DE602005006524D1 (de) * 2004-01-13 2008-06-19 Nxp Bv Jtag-testarchitektur für ein mehrchip-pack
KR20060133581A (ko) 2004-02-19 2006-12-26 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 전자 신호 처리 회로 및 이의 테스트 방법
WO2005086940A2 (en) * 2004-03-11 2005-09-22 Interdigital Technology Corporation Control of device operation within an area
US20060159440A1 (en) * 2004-11-29 2006-07-20 Interdigital Technology Corporation Method and apparatus for disrupting an autofocusing mechanism
US20060137018A1 (en) * 2004-11-29 2006-06-22 Interdigital Technology Corporation Method and apparatus to provide secured surveillance data to authorized entities
TW200730836A (en) * 2004-12-06 2007-08-16 Interdigital Tech Corp Method and apparatus for detecting portable electronic device functionality
US7574220B2 (en) * 2004-12-06 2009-08-11 Interdigital Technology Corporation Method and apparatus for alerting a target that it is subject to sensing and restricting access to sensed content associated with the target
US20060227640A1 (en) * 2004-12-06 2006-10-12 Interdigital Technology Corporation Sensing device with activation and sensing alert functions
EP1831789A2 (de) * 2004-12-20 2007-09-12 Koninklijke Philips Electronics N.V. Prüfbares mehrprozessorsystem und verfahren zum prüfen eines prozessorsystems
JP4388903B2 (ja) 2005-02-09 2009-12-24 富士通マイクロエレクトロニクス株式会社 Ｊｔａｇ試験方式
TW200708750A (en) 2005-07-22 2007-03-01 Koninkl Philips Electronics Nv Testable integrated circuit, system in package and test instruction set
JP2009512873A (ja) * 2005-10-24 2009-03-26 エヌエックスピー ビー ヴィ Ｉｃのテスト方法及び装置
EP1946131B1 (de) * 2005-11-02 2010-06-23 Nxp B.V. Ic-testverfahren und vorrichtungen
EP1791133A1 (de) * 2005-11-29 2007-05-30 STMicroelectronics Pvt. Ltd. Ein Verfahren zur gemeinsamen Nutzung von Testvorrichtungen für mehrere eingebettete Speicher und zugehöriges Speichersystem
US7579689B2 (en) * 2006-01-31 2009-08-25 Mediatek Inc. Integrated circuit package, and a method for producing an integrated circuit package having two dies with input and output terminals of integrated circuits of the dies directly addressable for testing of the package
WO2007119403A1 (ja) * 2006-03-16 2007-10-25 Matsushita Electric Industrial Co., Ltd. 端末装置
US7546498B1 (en) * 2006-06-02 2009-06-09 Lattice Semiconductor Corporation Programmable logic devices with custom identification systems and methods
US7620864B2 (en) * 2006-10-26 2009-11-17 International Business Machines Corporation Method and apparatus for controlling access to and/or exit from a portion of scan chain
KR100829402B1 (ko) * 2006-11-01 2008-05-15 주식회사 유니테스트 순차적 반도체 테스트 장치
US7657854B2 (en) * 2006-11-24 2010-02-02 Freescale Semiconductor, Inc. Method and system for designing test circuit in a system on chip
US8108744B2 (en) 2006-11-28 2012-01-31 Stmicroelectronics Pvt. Ltd. Locally synchronous shared BIST architecture for testing embedded memories with asynchronous interfaces
JP2008310792A (ja) * 2007-05-11 2008-12-25 Nec Electronics Corp テスト回路
US7937631B2 (en) * 2007-08-28 2011-05-03 Qimonda Ag Method for self-test and self-repair in a multi-chip package environment
US7904770B2 (en) * 2008-09-09 2011-03-08 Qualcomm Incorporated Testing circuit split between tiers of through silicon stacking chips
EP2372379B1 (de) * 2010-03-26 2013-01-23 Imec Testzugriffsarchitektur für TSV-basierte 3D-gestapelte ICS
KR101035399B1 (ko) * 2010-10-19 2011-05-20 (주)청석엔지니어링 폐타이어 고분자가 함유된 자착식 부틸합성고무 시트 방수제 및 이를 이용한 방수공법
KR101010358B1 (ko) * 2010-10-19 2011-01-25 (주)청석엔지니어링 종횡 방향 부직포가 부착된 부틸합성고무 시트 방수제 및 이를 이용한 방수공법
TW201221981A (en) * 2010-11-24 2012-06-01 Inventec Corp Multi-chip testing system and testing method thereof
US20130086441A1 (en) * 2011-09-30 2013-04-04 Qualcomm Incorporated Dynamically self-reconfigurable daisy-chain of tap controllers
DE102012210408A1 (de) * 2012-06-20 2013-12-24 Robert Bosch Gmbh Verfahren zum Ansteuern einer Zustandsmaschine
US9026872B2 (en) * 2012-08-16 2015-05-05 Xilinx, Inc. Flexible sized die for use in multi-die integrated circuit
US9063734B2 (en) 2012-09-07 2015-06-23 Atmel Corporation Microcontroller input/output connector state retention in low-power modes
US9250690B2 (en) * 2012-09-10 2016-02-02 Atmel Corporation Low-power modes of microcontroller operation with access to configurable input/output connectors
US9547034B2 (en) 2013-07-03 2017-01-17 Xilinx, Inc. Monolithic integrated circuit die having modular die regions stitched together
GB2518866A (en) * 2013-10-03 2015-04-08 St Microelectronics Res & Dev Flexible interface
DE112014006751T5 (de) * 2014-06-19 2017-03-23 X-Fab Semiconductor Foundries Ag Schlankes serielles Interface für ein Wrapper-Boundary-Register (vorrichtung und Verfahren)
US9557383B2 (en) 2014-12-12 2017-01-31 International Business Machines Corporation Partitioned scan chain diagnostics using multiple bypass structures and injection points
US9429621B2 (en) 2015-01-27 2016-08-30 International Business Machines Corporation Implementing enhanced scan chain diagnostics via bypass multiplexing structure
US9964597B2 (en) * 2016-09-01 2018-05-08 Texas Instruments Incorporated Self test for safety logic
KR101890030B1 (ko) * 2016-09-02 2018-08-20 주식회사 아이닉스 체인 형태로 연결된 디바이스 및 그 설정 방법
CN110825439B (zh) * 2018-08-10 2021-03-09 北京百度网讯科技有限公司 信息处理方法和处理器
US11249134B1 (en) * 2020-10-06 2022-02-15 Qualcomm Incorporated Power-collapsible boundary scan
CN112098818B (zh) * 2020-11-02 2021-02-02 创意电子(南京)有限公司 一种基于标准边界扫描电路的sip器件测试系统

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TW253031B (de) * 1993-12-27 1995-08-01 At & T Corp
US5615217A (en) * 1994-12-01 1997-03-25 International Business Machines Corporation Boundary-scan bypass circuit for integrated circuit electronic component and circuit boards incorporating such circuits and components
DE69734379T2 (de) * 1996-08-30 2006-07-06 Texas Instruments Inc., Dallas Vorrichtung zur Prüfung von integrierten Schaltungen
JPH1183956A (ja) * 1997-06-30 1999-03-26 Texas Instr Inc <Ti> 集積回路
US6032279A (en) * 1997-11-07 2000-02-29 Atmel Corporation Boundary scan system with address dependent instructions
KR19990047438A (ko) * 1997-12-04 1999-07-05 윤종용 핀 공유를 이용한 바이패스 회로를 구비하는 반도체 장치

Also Published As

Publication number Publication date
DE60218498T2 (de) 2007-11-08
KR100896538B1 (ko) 2009-05-07
JP4249019B2 (ja) 2009-04-02
CN1555491A (zh) 2004-12-15
WO2003025595A2 (en) 2003-03-27
TWI232951B (en) 2005-05-21
CN100342241C (zh) 2007-10-10
US20030079166A1 (en) 2003-04-24
JP2005503563A (ja) 2005-02-03
ATE355534T1 (de) 2006-03-15
EP1430319B1 (de) 2007-02-28
KR20040035848A (ko) 2004-04-29
WO2003025595A3 (en) 2003-08-28
US6988230B2 (en) 2006-01-17
EP1430319A2 (de) 2004-06-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL

8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN