DE602005006524D1 - Jtag-testarchitektur für ein mehrchip-pack - Google Patents

Jtag-testarchitektur für ein mehrchip-pack

Info

Publication number
DE602005006524D1
DE602005006524D1 DE602005006524T DE602005006524T DE602005006524D1 DE 602005006524 D1 DE602005006524 D1 DE 602005006524D1 DE 602005006524 T DE602005006524 T DE 602005006524T DE 602005006524 T DE602005006524 T DE 602005006524T DE 602005006524 D1 DE602005006524 D1 DE 602005006524D1
Authority
DE
Germany
Prior art keywords
chip
jtag
test architecture
jtag test
multiple pack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005006524T
Other languages
English (en)
Inventor
Jacky Talayssat
Sake Buwalda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602005006524D1 publication Critical patent/DE602005006524D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE602005006524T 2004-01-13 2005-01-05 Jtag-testarchitektur für ein mehrchip-pack Active DE602005006524D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04300016 2004-01-13
PCT/IB2005/000072 WO2005069025A1 (en) 2004-01-13 2005-01-05 Jtag test architecture for multi-chip pack

Publications (1)

Publication Number Publication Date
DE602005006524D1 true DE602005006524D1 (de) 2008-06-19

Family

ID=34778231

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005006524T Active DE602005006524D1 (de) 2004-01-13 2005-01-05 Jtag-testarchitektur für ein mehrchip-pack

Country Status (8)

Country Link
US (1) US7917819B2 (de)
EP (1) EP1706752B1 (de)
JP (1) JP2007518093A (de)
KR (1) KR101118447B1 (de)
CN (1) CN100545668C (de)
AT (1) ATE394683T1 (de)
DE (1) DE602005006524D1 (de)
WO (1) WO2005069025A1 (de)

Families Citing this family (20)

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US20070081396A1 (en) * 2005-10-06 2007-04-12 Gordon Tarl S System and method for multi-use eFuse macro
CN101078746B (zh) * 2007-07-11 2010-06-23 凤凰微电子（中国）有限公司 多芯片封装体内部连接的边界扫描测试结构及测试方法
KR101565724B1 (ko) 2007-08-08 2015-11-03 유니버셜 디스플레이 코포레이션 트리페닐렌기를 포함하는 벤조 융합 티오펜 또는 벤조 융합 푸란 화합물
US7958283B2 (en) * 2008-08-13 2011-06-07 Intel Corporation Observing an internal link via a second link
US8977788B2 (en) 2008-08-13 2015-03-10 Intel Corporation Observing an internal link via an existing port for system on chip devices
US8829940B2 (en) 2008-09-26 2014-09-09 Nxp, B.V. Method for testing a partially assembled multi-die device, integrated circuit die and multi-die device
US8572433B2 (en) * 2010-03-10 2013-10-29 Texas Instruments Incorporated JTAG IC with commandable circuit controlling data register control router
CN101865976A (zh) * 2009-04-14 2010-10-20 鸿富锦精密工业（深圳）有限公司 边界扫描测试系统及测试方法
TW201221981A (en) * 2010-11-24 2012-06-01 Inventec Corp Multi-chip testing system and testing method thereof
US8726109B2 (en) * 2011-05-02 2014-05-13 New York University Architecture, system, method, and computer-accessible medium for eliminating scan performance penalty
US8645777B2 (en) 2011-12-29 2014-02-04 Intel Corporation Boundary scan chain for stacked memory
US8914693B2 (en) 2012-02-15 2014-12-16 International Business Machines Corporation Apparatus for JTAG-driven remote scanning
CN104020409A (zh) * 2013-02-28 2014-09-03 中兴通讯股份有限公司 一种自适应配置芯片的方法及装置
US20160163609A1 (en) * 2014-12-03 2016-06-09 Altera Corporation Methods and apparatus for testing auxiliary components in a multichip package
US9780316B2 (en) 2015-03-16 2017-10-03 Universal Display Corporation Organic electroluminescent materials and devices
KR102566994B1 (ko) 2015-12-14 2023-08-14 삼성전자주식회사 멀티 칩 디버깅 방법 및 이를 적용하는 멀티 칩 시스템
CN106918750A (zh) * 2015-12-24 2017-07-04 英业达科技有限公司 适用于内存插槽的测试电路板
CN106918725A (zh) * 2015-12-25 2017-07-04 英业达科技有限公司 具联合测试工作群组信号串接电路设计的测试电路板
US10393805B2 (en) 2017-12-01 2019-08-27 International Business Machines Corporation JTAG support over a broadcast bus in a distributed memory buffer system
CN116699371B (zh) * 2023-08-08 2023-11-21 北京燧原智能科技有限公司 一种多芯片封装的老化测试方法和老化测试电路

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5043986A (en) 1989-05-18 1991-08-27 At&T Bell Laboratories Method and integrated circuit adapted for partial scan testability
TW253031B (de) * 1993-12-27 1995-08-01 At & T Corp
US5448525A (en) * 1994-03-10 1995-09-05 Intel Corporation Apparatus for configuring a subset of an integrated circuit having boundary scan circuitry connected in series and a method thereof
US5862152A (en) * 1995-11-13 1999-01-19 Motorola, Inc. Hierarchically managed boundary-scan testable module and method
US5625631A (en) * 1996-04-26 1997-04-29 International Business Machines Corporation Pass through mode for multi-chip-module die
US5907562A (en) * 1996-07-31 1999-05-25 Nokia Mobile Phones Limited Testable integrated circuit with reduced power dissipation
US5754410A (en) * 1996-09-11 1998-05-19 International Business Machines Corporation Multi-chip module with accessible test pads
US6032278A (en) 1996-12-26 2000-02-29 Intel Corporation Method and apparatus for performing scan testing
US6691267B1 (en) * 1997-06-10 2004-02-10 Altera Corporation Technique to test an integrated circuit using fewer pins
US6397361B1 (en) * 1999-04-02 2002-05-28 International Business Machines Corporation Reduced-pin integrated circuit I/O test
KR100363080B1 (ko) * 1999-06-15 2002-11-30 삼성전자 주식회사 단일 칩 병렬 테스팅 장치 및 방법
JP3763385B2 (ja) * 1999-11-09 2006-04-05 シャープ株式会社 半導体装置
GB2379524A (en) 2001-09-06 2003-03-12 Nec Technologies Multiplexing pins on an ASIC
KR100896538B1 (ko) * 2001-09-20 2009-05-07 엔엑스피 비 브이 전자 장치

Also Published As

Publication number Publication date
EP1706752B1 (de) 2008-05-07
EP1706752A1 (de) 2006-10-04
WO2005069025A1 (en) 2005-07-28
ATE394683T1 (de) 2008-05-15
KR101118447B1 (ko) 2012-03-06
KR20060133547A (ko) 2006-12-26
US20080288839A1 (en) 2008-11-20
JP2007518093A (ja) 2007-07-05
US7917819B2 (en) 2011-03-29
CN100545668C (zh) 2009-09-30
CN1910464A (zh) 2007-02-07

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Legal Events

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