NO20083721L - High speed redundant data processing system - Google Patents

High speed redundant data processing system

Info

Publication number
NO20083721L
NO20083721L NO20083721A NO20083721A NO20083721L NO 20083721 L NO20083721 L NO 20083721L NO 20083721 A NO20083721 A NO 20083721A NO 20083721 A NO20083721 A NO 20083721A NO 20083721 L NO20083721 L NO 20083721L
Authority
NO
Norway
Prior art keywords
data processing
modules
checking
high speed
processing system
Prior art date
Application number
NO20083721A
Other languages
English (en)
Other versions
NO337469B1 (no
Inventor
Darren Stewart Learmonth
Original Assignee
Eads Defence And Security Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eads Defence And Security Systems Ltd filed Critical Eads Defence And Security Systems Ltd
Publication of NO20083721L publication Critical patent/NO20083721L/no
Publication of NO337469B1 publication Critical patent/NO337469B1/no

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1629Error detection by comparing the output of redundant processing systems
    • G06F11/1641Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G06F11/1645Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components and the comparison itself uses redundant hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Detection And Correction Of Errors (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

Det beskrives et databehandlingssystem med høy hastighet, omfattende en første og en andre databehandlingsmodul og en første og en andre datakontrollmodul. Den første og den andre databehandlingsmodul er hver for seg innrettet til å utføre i det vesentlige de samme behandlingstrinn på data mottatt ved en datainngang, og hver tilveiebringer utdata. Den første og den andre kontrollmodul er innrettet til å sammenligne utdataene fra nevnte første og andre databehandlingsmodul og til å avgi et feilsignal som angir om nevnte første og andre databehandlingsmodul har utført i det vesentlige de samme behandlingstrinn. Den første og den andre kontrollmodul befinner seg på fysisk atskilte anordninger. I noen arrangementer er det tilveiebrakt en tredje kontrollmodul, hvilken kontrollmodul kan være fysisk atskilt fra hver av nevnte første og andre kontrollmodul.
NO20083721A 2006-02-09 2008-08-29 Redundant databehandlingssystem med høy hastighet NO337469B1 (no)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0602641.3A GB0602641D0 (en) 2006-02-09 2006-02-09 High speed data processing system
PCT/GB2006/004720 WO2007091005A1 (en) 2006-02-09 2006-12-15 High speed redundant data processing system

Publications (2)

Publication Number Publication Date
NO20083721L true NO20083721L (no) 2008-11-05
NO337469B1 NO337469B1 (no) 2016-04-18

Family

ID=36119811

Family Applications (1)

Application Number Title Priority Date Filing Date
NO20083721A NO337469B1 (no) 2006-02-09 2008-08-29 Redundant databehandlingssystem med høy hastighet

Country Status (13)

Country Link
US (1) US8386843B2 (no)
EP (1) EP1989624B1 (no)
JP (1) JP5203223B2 (no)
AT (1) ATE456091T1 (no)
AU (1) AU2006337907B2 (no)
CA (1) CA2641682C (no)
DE (1) DE602006011961D1 (no)
DK (1) DK1989624T3 (no)
ES (1) ES2340720T3 (no)
GB (1) GB0602641D0 (no)
NO (1) NO337469B1 (no)
NZ (1) NZ570745A (no)
WO (1) WO2007091005A1 (no)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8548640B2 (en) * 2010-12-21 2013-10-01 Microsoft Corporation Home heating server
DE102011102274B4 (de) 2011-05-23 2012-12-06 Pilz Gmbh & Co. Kg Verfahren zum Betreiben eines Sicherheitssteuergeräts
US9778912B2 (en) 2011-05-27 2017-10-03 Cassy Holdings Llc Stochastic processing of an information stream by a processing architecture generated by operation of non-deterministic data used to select data processing modules
DE102012004844B4 (de) * 2012-03-13 2018-05-17 Phoenix Contact Gmbh & Co. Kg System der Messwertüberwachung und Abschaltung bei Auftreten von Messwertabweichungen
JP6036089B2 (ja) * 2012-09-25 2016-11-30 日本電気株式会社 データ遷移トレース装置、データ遷移トレース方法、及び、データ遷移トレースプログラム
CN106294044B (zh) * 2016-08-09 2019-05-03 上海东软载波微电子有限公司 芯片内部寄存器的校验电路及芯片
DE102018115759B3 (de) * 2018-06-29 2019-08-29 Scheidt & Bachmann Gmbh Balisensteuerungsvorrichtung

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE793400A (fr) 1972-03-13 1973-06-28 Siemens Ag Systeme de traitement de donnees commande par programme avec une exploitation parallele de deux unites identiques ou plus du systeme
DE2612100A1 (de) * 1976-03-22 1977-10-06 Siemens Ag Digitale datenverarbeitungsanordnung, insbesondere fuer die eisenbahnsicherungstechnik
US4358823A (en) * 1977-03-25 1982-11-09 Trw, Inc. Double redundant processor
DE3003291C2 (de) 1980-01-30 1983-02-24 Siemens AG, 1000 Berlin und 8000 München Zweikanalige Datenverarbeitungsanordnung für Eisenbahnsicherungszwecke
DE3412049A1 (de) 1984-03-30 1985-10-17 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Signaltechnisch sichere datenverarbeitungseinrichtung
JPS626263A (ja) * 1985-07-02 1987-01-13 Minolta Camera Co Ltd 積層型感光体
CH675781A5 (no) 1987-04-16 1990-10-31 Bbc Brown Boveri & Cie
DE3843564A1 (de) * 1988-12-23 1990-06-28 Standard Elektrik Lorenz Ag Verfahren zur ueberpruefung von verbindungs- und/oder schalteinrichtungen und/oder -leitungen
JPH02301836A (ja) 1989-05-17 1990-12-13 Toshiba Corp データ処理システム
US5086429A (en) * 1990-04-10 1992-02-04 Honeywell Inc. Fault-tolerant digital computing system with reduced memory redundancy
US5243607A (en) * 1990-06-25 1993-09-07 The Johns Hopkins University Method and apparatus for fault tolerance
US5226152A (en) * 1990-12-07 1993-07-06 Motorola, Inc. Functional lockstep arrangement for redundant processors
GB9205842D0 (en) 1992-03-18 1992-04-29 Marconi Gec Ltd Distributed processor arrangement
US5758058A (en) * 1993-03-31 1998-05-26 Intel Corporation Apparatus and method for initializing a master/checker fault detecting microprocessor
JPH07129426A (ja) 1993-10-29 1995-05-19 Hitachi Ltd 障害処理方式
JPH07160521A (ja) 1993-12-13 1995-06-23 Nec Corp 耐障害機能を有する情報処理装置
JPH07281915A (ja) 1994-04-08 1995-10-27 Mitsubishi Electric Corp 集積回路モジュール同期2重系情報処理装置
DE19529434B4 (de) 1995-08-10 2009-09-17 Continental Teves Ag & Co. Ohg Microprozessorsystem für sicherheitskritische Regelungen
JP3247043B2 (ja) 1996-01-12 2002-01-15 株式会社日立製作所 内部信号で障害検出を行う情報処理システムおよび論理lsi
GB9705436D0 (en) * 1997-03-15 1997-04-30 Sharp Kk Fault tolerant circuit arrangements
US6247118B1 (en) 1998-06-05 2001-06-12 Mcdonnell Douglas Corporation Systems and methods for transient error recovery in reduced instruction set computer processors via instruction retry
US7480242B2 (en) * 1998-11-24 2009-01-20 Pluris, Inc. Pass/drop apparatus and method for network switching node
US6601210B1 (en) * 1999-09-08 2003-07-29 Mellanox Technologies, Ltd Data integrity verification in a switching network
US6909923B2 (en) * 1999-12-22 2005-06-21 Rockwell Automation Technologies, Inc. Safety communication on a single backplane
GB0012352D0 (en) 2000-05-22 2000-07-12 Northern Telecom Ltd Reliable hardware support for the use of formal languages in high assurance systems
US6985975B1 (en) * 2001-06-29 2006-01-10 Sanera Systems, Inc. Packet lockstep system and method
US6898738B2 (en) * 2001-07-17 2005-05-24 Bull Hn Information Systems Inc. High integrity cache directory
GB2399913B (en) * 2002-03-19 2004-12-15 Sun Microsystems Inc Fault tolerant computer system
EP1398700A1 (de) 2002-09-12 2004-03-17 Siemens Aktiengesellschaft Verfahren und Schaltungsanordnung zur Synchronisation redundanter Verarbeitungseinheiten
EP1398699A1 (de) 2002-09-12 2004-03-17 Siemens Aktiengesellschaft Verfahren zur Ereignissynchronisation, insbesondere für Prozessoren fehlertoleranter Systeme
EP1398701A1 (de) 2002-09-12 2004-03-17 Siemens Aktiengesellschaft Verfahren zur Ereignissynchronisation, insbesondere für Prozessoren fehlertoleranter Systeme
US7213168B2 (en) * 2003-09-16 2007-05-01 Rockwell Automation Technologies, Inc. Safety controller providing for execution of standard and safety control programs
US7353365B2 (en) * 2004-09-29 2008-04-01 Intel Corporation Implementing check instructions in each thread within a redundant multithreading environments
US7979833B2 (en) * 2004-10-23 2011-07-12 Lsi Corporation Debugging simulation of a circuit core using pattern recorder, player and checker
US7350026B2 (en) * 2004-12-03 2008-03-25 Thales Memory based cross compare for cross checked systems
US7617412B2 (en) * 2006-10-25 2009-11-10 Rockwell Automation Technologies, Inc. Safety timer crosscheck diagnostic in a dual-CPU safety system

Also Published As

Publication number Publication date
JP2009526299A (ja) 2009-07-16
EP1989624B1 (en) 2010-01-20
US20100318851A1 (en) 2010-12-16
NO337469B1 (no) 2016-04-18
ES2340720T3 (es) 2010-06-08
JP5203223B2 (ja) 2013-06-05
GB0602641D0 (en) 2006-03-22
CA2641682A1 (en) 2007-08-16
EP1989624A1 (en) 2008-11-12
DK1989624T3 (da) 2010-05-17
US8386843B2 (en) 2013-02-26
NZ570745A (en) 2011-07-29
AU2006337907B2 (en) 2012-05-31
CA2641682C (en) 2015-04-21
AU2006337907A1 (en) 2007-08-16
DE602006011961D1 (de) 2010-03-11
WO2007091005A1 (en) 2007-08-16
ATE456091T1 (de) 2010-02-15

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Legal Events

Date Code Title Description
CHAD Change of the owner's name or address (par. 44 patent law, par. patentforskriften)

Owner name: AIRBUS DEFENCE AND SPACE LIMITED, GB