DE602007013954D1 - Chipprüfvorrichtung und verfahren zum bereitstellen von timinginformationen - Google Patents

Chipprüfvorrichtung und verfahren zum bereitstellen von timinginformationen

Info

Publication number
DE602007013954D1
DE602007013954D1 DE602007013954T DE602007013954T DE602007013954D1 DE 602007013954 D1 DE602007013954 D1 DE 602007013954D1 DE 602007013954 T DE602007013954 T DE 602007013954T DE 602007013954 T DE602007013954 T DE 602007013954T DE 602007013954 D1 DE602007013954 D1 DE 602007013954D1
Authority
DE
Germany
Prior art keywords
chip tester
under test
timing information
channel
propagation delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007013954T
Other languages
English (en)
Inventor
Michael Daub
Alf Clement
Bernd Laquai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Verigy Singapore Pte Ltd
Original Assignee
Verigy Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Verigy Singapore Pte Ltd filed Critical Verigy Singapore Pte Ltd
Publication of DE602007013954D1 publication Critical patent/DE602007013954D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Credit Cards Or The Like (AREA)
DE602007013954T 2007-08-22 2007-08-22 Chipprüfvorrichtung und verfahren zum bereitstellen von timinginformationen Active DE602007013954D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2007/007388 WO2009024173A1 (en) 2007-08-22 2007-08-22 Chip tester, method for providing timing information, test fixture set, apparatus for post-processing propagation delay information, method for post-processing delay information, chip test set up and method for testing devices under test

Publications (1)

Publication Number Publication Date
DE602007013954D1 true DE602007013954D1 (de) 2011-05-26

Family

ID=39415293

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007013954T Active DE602007013954D1 (de) 2007-08-22 2007-08-22 Chipprüfvorrichtung und verfahren zum bereitstellen von timinginformationen

Country Status (8)

Country Link
US (1) US8326565B2 (de)
EP (1) EP2142936B1 (de)
JP (1) JP2010537174A (de)
KR (1) KR101225235B1 (de)
CN (1) CN101784906B (de)
AT (1) ATE505734T1 (de)
DE (1) DE602007013954D1 (de)
WO (1) WO2009024173A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103003708B (zh) * 2010-04-14 2015-01-07 爱德万测试(新加坡)私人有限公司 用于测试多个被测器件的装置和方法
DE102013002087B4 (de) * 2012-02-24 2020-01-30 Infineon Technologies Ag Verfahren und System zum Ausgleichen einer Verzögerungsabweichung zwischen einem ersten Messkanal und einem zweiten Messkanal
KR101379265B1 (ko) * 2012-09-04 2014-03-28 삼성중공업 주식회사 칩 정보 획득 장치 및 방법
JP2015040795A (ja) * 2013-08-22 2015-03-02 住友電工デバイス・イノベーション株式会社 試験装置
WO2016173619A1 (en) 2015-04-27 2016-11-03 Advantest Corporation Switch circuit, method for operating a switch circuit and an automated test equipment
WO2016188572A1 (en) 2015-05-27 2016-12-01 Advantest Corporation Automated test equipment for combined signals
US10429437B2 (en) * 2015-05-28 2019-10-01 Keysight Technologies, Inc. Automatically generated test diagram
KR102626858B1 (ko) * 2016-11-02 2024-01-19 삼성전자주식회사 전송 선로의 전파 지연 시간을 측정하기 위한 테스트 시스템
KR20200016680A (ko) 2018-08-07 2020-02-17 삼성전자주식회사 피크 노이즈를 감소한 테스트 장치, 테스트 방법 및 테스트가 수행되는 반도체 장치
KR20220037283A (ko) 2020-09-17 2022-03-24 삼성전자주식회사 테스트 보드 및 이를 포함하는 반도체 소자 테스트 시스템
CN116685854A (zh) * 2021-03-09 2023-09-01 华为技术有限公司 一种时延参数的检验方法和装置
CN115878437A (zh) * 2021-09-28 2023-03-31 华为技术有限公司 应用的性能测试方法、建立性能测试模型的方法及装置
CN116068380B (zh) * 2023-03-01 2023-07-07 上海聚跃检测技术有限公司 一种芯片封装测试方法及装置
CN117452187A (zh) * 2023-11-15 2024-01-26 广东高云半导体科技股份有限公司 一种io延迟测试电路及方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5727021A (en) 1996-04-03 1998-03-10 Teradyne, Inc. Apparatus and method for providing a programmable delay with low fixed delay
JP2000314764A (ja) * 1999-05-06 2000-11-14 Advantest Corp Ｉｃ試験装置のタイミング校正方法及びこの校正方法に用いるショートデバイス
JP2001014900A (ja) * 1999-06-29 2001-01-19 Fujitsu Ltd 半導体装置及び記録媒体
KR100487946B1 (ko) * 2002-08-29 2005-05-06 삼성전자주식회사 반도체 테스트 시스템 및 이 시스템의 테스트 방법
DE10338079B4 (de) * 2003-08-19 2007-05-16 Infineon Technologies Ag Testanordnung zum Testen von Halbleiterschaltungschips
JP4025731B2 (ja) * 2004-01-26 2007-12-26 エルピーダメモリ株式会社 タイミング補正装置、タイミング補正方法及びデバイス評価装置
US7210074B2 (en) 2005-06-23 2007-04-24 Agilent Technologies, Inc Built-in waveform edge deskew using digital-locked loops and coincidence detectors in an automated test equipment system
US7281181B2 (en) * 2005-06-27 2007-10-09 Verigy (Singapore) Pte. Ltd. Systems, methods and computer programs for calibrating an automated circuit test system
KR20080014995A (ko) * 2005-08-09 2008-02-15 가부시키가이샤 아드반테스트 반도체 시험 장치
KR100738676B1 (ko) 2006-04-13 2007-07-11 한국과학기술원 난분해성 폐수의 습식산화를 위한 세리아-지르코니아계전이금속 촉매
KR100736676B1 (ko) * 2006-08-01 2007-07-06 주식회사 유니테스트 반도체 소자 테스트 장치

Also Published As

Publication number Publication date
ATE505734T1 (de) 2011-04-15
EP2142936A1 (de) 2010-01-13
WO2009024173A1 (en) 2009-02-26
KR20100043083A (ko) 2010-04-27
KR101225235B1 (ko) 2013-01-23
JP2010537174A (ja) 2010-12-02
EP2142936B1 (de) 2011-04-13
CN101784906B (zh) 2014-03-12
CN101784906A (zh) 2010-07-21
US8326565B2 (en) 2012-12-04
US20110131000A1 (en) 2011-06-02

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