US8326565B2 - Chip tester, method for providing timing information, test fixture set, apparatus for post-processing propagation delay information, method for post-processing delay information, chip test set up and method for testing devices under test - Google Patents

Chip tester, method for providing timing information, test fixture set, apparatus for post-processing propagation delay information, method for post-processing delay information, chip test set up and method for testing devices under test Download PDF

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US8326565B2
US8326565B2 US12/674,644 US67464410A US8326565B2 US 8326565 B2 US8326565 B2 US 8326565B2 US 67464410 A US67464410 A US 67464410A US 8326565 B2 US8326565 B2 US 8326565B2
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under test
device under
chip tester
contact element
channel
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US20110131000A1 (en
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Michael Daub
Alf Clement
Bernd Laquai
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Advantest Corp
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Advantest Singapore Pte Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration

Definitions

  • the present invention is generally related to a chip tester, a method for providing timing information, a test fixture set, an apparatus for post-processing propagation delay information, a method for post-processing delay information, a chip test set up and a method for testing devices under test.
  • the present invention is related to a fixture delay calibration in a driver sharing test environment.
  • terminals of at least two devices under test are connected to a common channel of a chip tester. These terminals are typically designated as shared terminals. However, some of the terminals of the devices under test are connected to channels of the chip tester via individual (non-shared or unshared) lines. Thus, in typical setups there are both shared terminals of devices under test, which are connected to the chip tester via a shared line and unshared terminals, which are connected to channels of the chip tester via unshared lines.
  • a chip tester for testing at least two devices under test connected to the chip tester wherein at least a first terminal of the a first device under test and a first terminal of a second device under test are connected to a first channel of the chip tester via a shared line, wherein a second terminal of the first device under test is connected to a second channel of the chip tester via an unshared line, and wherein a second terminal of the second device under test is connected to a third channel of the chip tester via an unshared line
  • the timing calculator for generating a timing information for the channels of the chip tester, wherein the timing calculator is adapted to acquire a propagation delay difference information describing a difference between, on the one hand, a propagation delay from a first channel port of the chip tester to the first terminal of the first device under test and, on the other hand, a propagation delay from the first channel port of the chip tester to the first terminal of the second device under test, and wherein the timing calculator is adapted to provide timing information to adjust a timing shift
  • a test fixture set may have a device under test board for providing an electrical connection between a chip tester and at least two devices under test, wherein device under test board may have a first device under test contact element for providing a detachable electrical contact between the device under test board and a first device under test, a second device under test contact element for providing a detachable electrical contact between the device under test board and a second device under test, a third device under test contact element for providing a detachable electrical contact between the device under test board and the first device under test, a fourth device under test contact element for providing a detachable electrical contact between the device under test board and the second device under test, a first chip tester contact element for providing a detachable electrical contact between the device under test board and the chip tester, a second chip tester contact element for providing a detachable electrical contact between the device under test board and the chip tester, and a third chip tester contact element for providing a detachable electrical contact between the device under test board and the chip tester,
  • an apparatus for post-processing a plurality of propagation delay values of a device under test board for a chip tester wherein the device under test board is adapted to provide an electrical connection between a chip tester and at least two devices under test, and wherein the device under test board has a first device under test contact element for providing a detachable electrical contact between the device under test board and a first device under test, a second device under test contact element for providing a detachable electrical contact between the device under test board and a second device under test, a third device under test contact element for providing a detachable electrical contact between the device under test board and the first device under test, a fourth device under test contact element for providing a detachable electrical contact between the device under test board and the second device under test, a first chip tester contact element for providing a detachable contact between the device under test board and the chip tester, a second chip tester contact element for providing a detachable contact between the device under test board and the chip tester, a third chip
  • a method for providing timing information for adjusting a timing of a chip tester operating in a configuration in which at least a first terminal of a first device under test and a first terminal of a second device under test are connected to a first channel of the chip tester via a shared line and in which a second terminal of the first device under test is connected to a second channel of the chip tester via an unshared line and in which a second terminal of the second device under test is connected to a third channel of the chip tester via an unshared line, may have the steps of acquiring a propagation delay difference information describing a propagation time difference between, on the one hand, the propagation delay from a first channel port of the chip tester to the first terminal of the first device under test, and, on the other hand, a propagation delay from the first channel port of the chip tester to the first terminal of the second device under test; and providing the timing information to adjust a timing shift between timings of the second channel and the third channel on the basis of the propagation time difference information.
  • a method for post-processing a plurality of propagation delay values for a device under test board for a chip tester wherein the device under test board is adapted to provide an electrical connection between the chip tester and at least two devices under test, and wherein the device under test board has a first device under test contact element for providing a detachable electrical contact between the device under test board and a first device under test, a second device under test contact element for providing a detachable electrical contact between the device under test board and a second device under test, a third device under test contact element for providing a detachable electrical contact between the device under test board and the first device under test, a fourth device under test contact element for providing a detachable electrical contact between the device under test board and the second device under test, a first chip tester contact element for providing a detachable electrical contact between the device under test board and the chip tester, a second chip tester contact element for providing a detachable electrical contact between the device under test board and the chip tester, and
  • An embodiment of the present invention creates a chip tester for testing at least two devices under test.
  • the chip tester comprises a first channel and a second channel, a timing calculator for generating a timing information for the channels of the chip tester and a channel module configurator.
  • the timing calculator is adapted to generate a timing information for the channels of the chip tester, and is further adapted to obtain a propagation delay difference information describing a difference between, on the one hand, a propagation delay from a first channel port of the chip tester to a first terminal of the first device under test (DUT) and, on the other hand, a propagation delay from the first channel port of the chip tester to a first terminal of a second device under test.
  • the timing calculator is adapted to provide a timing information for a second channel of the chip tester connected to the first device under test or to the second device under test on the basis of the propagation delay difference information.
  • the channel module configurator is adapted to configure the second channel of the chip tester on the basis of the timing information.
  • FIG. 1 shows a schematic diagram of a chip tester, according to an embodiment of the present invention
  • FIGS. 2 a to 2 c show possible configurations of two devices under test, according to embodiments of the present invention
  • FIG. 3 shows a block schematic diagram of a chip tester, connected to two devices under test, according to an embodiment of the present invention
  • FIG. 4 a shows a graphical representation of an exemplary wave form, which may be present at a channel port of a chip tester according to an embodiment of the present invention
  • FIG. 4 b shows a graphical representation of an exemplary wave form, which may be present at a channel port of a chip tester according to an embodiment of the present invention
  • FIG. 4 c shows a graphical representation of an exemplary wave form, which may be present at a channel port of a chip tester according to an embodiment of the present invention
  • FIG. 4 d shows a graphical representation of exemplary wave forms, which may be present at the channel ports of a chip tester according to an embodiment of the present invention
  • FIG. 4 e shows a graphical representation of exemplary wave forms, which may be present at terminals of the first device under test according to an embodiment of the present invention
  • FIG. 4 f shows a graphical representation of exemplary wave forms, which may be present at terminals of the second device under test according to an embodiment of the present invention
  • FIG. 5 shows a graphical representation of an output wave form and a sample reference time, which may be present in a chip tester according to an embodiment of the present invention
  • FIG. 6 shows a block schematic diagram of an apparatus for post processing propagation delay values, according to an embodiment of the present invention
  • FIG. 7 a shows a graphical representation of an actual dut board and possible corresponding original propagation delay value files, according to an embodiment of the present invention
  • FIG. 7 b shows a graphical representation of a possible effective dut board and a possible corresponding effective propagation delay value file, according to an embodiment of the present invention
  • FIG. 7 c shows a graphical representation of another possible effective device under test board and possible corresponding effective propagation delay value files, according to an embodiment of the present invention.
  • FIG. 7 d shows an example of an extended configuration for testing two duts
  • FIG. 8 shows a graphical representation of an averaging scheme for determining an average propagation delay difference value, according to an embodiment of the present invention
  • FIG. 9 shows a graphical representation of a dut board set, according to an embodiment of the present invention.
  • FIG. 10 shows a graphical representation of a dut board comprising more than 2 devices under test, according to an embodiment of the present invention
  • FIG. 11 shows a flow chart of an inventive method for characterizing a dut board
  • FIG. 12 shows a flow chart of a method for providing timing information for adjusting a timing of a chip tester, according to an embodiment of the present invention.
  • FIG. 1 shows a block schematic diagram of a chip tester according to an embodiment of the present invention.
  • the chip tester of FIG. 1 is designated in its entirety with 100 .
  • the chip tester 100 comprises a timing calculator 110 , which is adapted to obtain (e.g. to read or to measure) a propagation delay difference information 112 .
  • the timing calculator 110 is further adapted to provide a timing information 114 to a channel module configurator 120 .
  • the chip tester 100 further comprises a first channel 130 and a second channel 132 , wherein a dut terminal of the first channel 130 is routed to a first channel port 134 , and wherein a dut terminal of the second channel 132 is routed to a second channel port 136 .
  • the second channel 132 is cabled to the channel module configurator 120 to receive timing configuration information 140 from the channel module configurator 120 .
  • the first channel 130 may also be connected to the channel module configurator 120 .
  • FIG. 1 shows a first device under test 150 and a second device under test 160 , which are connected to the chip tester 100 .
  • the devices under test 150 , 160 are naturally not part of the chip tester.
  • a first terminal 152 of the first device under test 150 is connected to the first terminal port 134 of the chip tester 100
  • the first terminal 162 of the second device under test 160 is also connected to the first channel port 134 of the chip tester 100 .
  • a second terminal 164 of the second device under test 160 (which may be an input terminal or an output terminal, or an input/output terminal) is cabled to the second channel port 136 of the chip tester 100 .
  • a second terminal 154 of the first device under test 150 (which may be an input terminal or an output terminal, or an input/output terminal) is connected to the second channel port 136 .
  • the propagation delay difference information 112 describes the difference between, on the one hand, a propagation delay from the first channel port 134 of the chip tester to the first terminal 152 of the first device under test 150 , and, on the other hand, a propagation delay from the first channel port 134 of the chip tester to a first terminal 162 of the second device under test.
  • the timing calculator of the chip tester handles information about a difference of propagation delays of a signal output at the first channel port 134 traveling to the first device under test 150 and to the second device under test 160 .
  • the timing calculator 110 is adapted to provide a timing information for the second channel 132 of a chip tester on the basis of the propagation delay difference information 112 .
  • the channel module configurator is adapted to configure the second channel 132 of the chip tester 110 on the basis of the timing information 114 .
  • a timing of the second channel 132 can be adapted in dependence on the propagation delay difference information 112 .
  • an appropriate timing of the signals reaching the devices under test can be achieved, in spite of the different propagation delay times between the first channel port and the terminals 152 , 162 of the first device under test 150 and the second device under test 160 .
  • the second channel 132 can either be an input channel, an output channel (also designated as driver channel) or an input/output channel. Moreover, it should be noted that the second channel 132 can be an input/output channel configured to act either as an input channel only or as an output channel only.
  • FIG. 2 a shows a block schematic diagram of a first dut configuration.
  • a first dut 150 a comprises a first input terminal 152 a and a second input terminal 154 a .
  • a second device under test 160 a comprises a first input terminal 162 a and a second input terminal 164 a .
  • the first input terminal 152 a of the first dut 150 a and the first input terminal 162 a of the second dut 160 a are both connected to an output channel (driver channel) 130 a of a chip tester.
  • the second input port 154 a of the first dut 150 a is cabled (or electrically connected) to a second output port 132 a of a chip tester.
  • the second input port 164 a of the second dut 160 a is further connected to a third output port 138 a of the chip tester. Moreover, a propagation delay between the output channel (driver channel) 130 a (or a corresponding channel port) and the input terminal 152 a of the first dut 150 is designated with ⁇ tp 1 . A propagation delay between the output channel (driver channel) 130 a (or a corresponding channel port) and the first input terminal 162 a of the second dut 160 a is designated with ⁇ tp 2 .
  • duts 150 a , 160 a may also comprise outputs, which are not shown here for the sake of simplicity. Signals, which may be present at the dut outputs may, for example, be input into the chip tester, and may further be used in order to decide whether a dut fulfills a desired specification.
  • first output channel (driver channel) 130 a may, in an embodiment, be identical to the first channel 130 .
  • the second output channel (driver channel) 132 a may be identical to the second channel 132 .
  • FIG. 2 b shows a block schematic diagram of another dut configuration.
  • a first dut 150 b comprises an input terminal 152 b and an output terminal 154 b .
  • a second dut 160 b comprises an input terminal 162 b and an output terminal 164 b .
  • the input terminals 152 b , 162 b of the first and second dut 150 b , 160 b are both connected to a an output channel 130 b of a chip tester.
  • Propagation delays between the output channel 130 b and the input terminals 152 b , 162 b are again designated with ⁇ tp 1 and ⁇ tp 2 .
  • the output terminal 154 b of the first dut 150 b is coupled (or electrically connected) with a first input channel 132 b (or an input/output channel configured as an input) of the chip tester.
  • the output terminal 164 b of the second dut 160 is coupled to an input channel (or input/output channel configured as an input) 138 b of the chip tester.
  • the output channel 130 b may be identical to the first channel 130 and that the input channel 132 b may be identical to the second channel 132 .
  • FIG. 2 c shows a graphical representation of another dut configuration, which may, for example, be used for testing high speed duts.
  • FIG. 2 c shows a configuration in which some of the input pins of the duts are shared and in which each dut further comprises at least one unshared input and at least one unshared output.
  • a first dut 150 c comprises a first shared input 152 c , a second shared input 153 c , a first unshared input 154 c , a second unshared input 155 c , a first output 156 c and a second output 157 c .
  • a second dut 160 c comprises a corresponding first shared input 162 c , a second shared input 163 c , a first unshared input 164 c , a second unshared input 165 c , a first output 166 c , and a second output 167 c .
  • the first shared input 152 c of the first dut 150 c and the first shared input 162 c of the second dut 160 c are both connected, using a first shared bus line 170 c , with a first output channel 134 c of the chip tester.
  • the second shared input 153 c of the first dut 150 c and the second shared input 163 c of the second dut 160 c are both connected with an output channel 135 c of the chip tester using a second shared bus line 171 c .
  • the first output 156 c of the first dut 150 c is connected with a first input channel 172 c of the chip tester
  • the second output 157 c of the first dut 150 c is connected with a second input channel 173 c of the chip tester
  • the first output 166 c of the second dut 160 c is connected with a third input channel 174 c of the chip tester
  • the second output 167 c of the second dut 160 c is connected with a fourth input channel 175 c of the chip tester.
  • the first unshared input 154 c of the first dut 150 c is connected with a third output channel 176 c of the chip tester, the second unshared input 155 c of the first dut 150 c is connected with a fourth output channel 177 c of the chip tester, the first unshared input 164 c of the second dut 160 c is connected with a fifth output channel 178 c of the chip tester and the second unshared input 165 c of the second dut 160 c is connected with a sixth output channel 179 c of the chip tester.
  • each of the duts 150 c , 160 c comprises at least 1 (in the example: 2) shared inputs, wherein a shared input of the first dut 150 c and a shared input of the second dut 160 c are connected to the same output channel of the chip tester.
  • Outputs of the duts 150 c , 160 c are connected individually to input channels of the chip tester.
  • the input channels comprise respective tester receivers.
  • at least one output of the first dut 150 c is connected to an input channel of the chip tester.
  • the duts 150 c , 160 c comprise at least 1 (in the example: 2) unshared inputs, which are connected individually to corresponding output channels of the chip tester.
  • there is at least one output channel of the chip tester which is cabled to an input of only one device under test out of the first device under test and the second device under test.
  • Such an output channel of the chip tester in the following will also be designated as an unshared test channel.
  • a first unshared test channel of the chip tester is connected to an input terminal of the first device under test 150 c but not to an input terminal of the second device under test 160 c
  • a second unshared test channel of the chip tester is connected to an input terminal of the second device under test 160 c but not to an input terminal of the first dut 150 c.
  • tester output channel is also briefly designated as tester driver.
  • tester input channel is briefly designated as tester receiver.
  • the shared bus lines 170 c , 171 c are optionally terminated.
  • a termination of a shared bus line 170 c , 171 c can, for example, comprise a termination resistance 180 c , 182 c .
  • the termination may optionally further comprise a termination voltage source 181 c , 183 c.
  • FIGS. 2 a , 2 b and 2 c may be implemented on a device under test board (dut board), wherein the connections between the channels of the chip tester and the duts comprise transmission lines, routed on the dut board, and electrical connectors adapted to provide an electrical connection between the dut board and terminals of the duts.
  • Electrical connectors may, for example, be test sockets for providing a detachable electrical connection.
  • the electrical connectors may also comprise nails or tips adapted to provide an electrical connection. However, any other types of connectors may be used.
  • driver sharing i.e.
  • dut interface or dut board
  • two categories of device input pins or device input terminals may be distinguished: input pins (or input terminals) connected to unshared tester driver channels or unshared tester output channels (so-called unshared dut inputs) and input pins (or input terminals) connected to shared tester driver channels or shared tester output channels (so-called shared dut inputs).
  • the receiver channels are not shared.
  • Unshared inputs of a device (or dut) are conventional input pins that are connected 1:1 to a tester driver channel or tester output channel.
  • shared inputs of a device are connected to lines of a shared bus.
  • the shared inputs of a group of N devices are connected to one shared bus (or shared bus line).
  • each line of the shared bus is connected to one tester driver channel. Therefore, in an embodiment, one tester driver channel drives N shared inputs.
  • multiple shared buses may exist on a dut interface (or dut board) to accommodate the parallel testing of M devices.
  • the lines of a shared bus are operated as terminated transmission lines to achieve high speed.
  • the N shared inputs connected to one line of the bus form taps to the transmission line.
  • each input comes with a parasitic load which causes distortions on the signals that propagate along the shared bus. Therefore, in an embodiment of the invention, when driver sharing is implemented to test memory devices, only the lower speed signals, such as command and control inputs, are operated as shared inputs.
  • the concept may also be used with other devices.
  • FIGS. 2 a , 2 b and 2 c A driver sharing by ⁇ 2 implementing the principle described above is illustrated in FIGS. 2 a , 2 b and 2 c.
  • a dut interface or dut board that implements driver sharing for a memory device contains K socket boards for N devices on each board. Therefore, each of said socket boards implements one shared bus.
  • the shared bus as well as unshared inputs of a device are connected to a mother board with cables (wherein the motherboard may provide the connection between the cables and channel modules of the chip tester).
  • a fixture delay calibration is performed to compensate the propagation delays induced by the long signal path on the interface (or dut board).
  • the existence of the shared bus on the socket board (or dut board) has to be taken into account when performing the fixture delay calibration.
  • the fixture delay values for the driver channel driving the shared bus are only valid for the first dut (DUT 1 ).
  • the term “fixture delay value” may designate a propagation delay between chip tester ports (also designated as chip tester contact elements) of the dut board and dut terminals (or dut contact elements) of the dut board.
  • the term “fixture delay value” may also designate a total propagation delay between a chip tester channel port and a dut terminal (or dut contact element) of the dut board.
  • an additional delay occurs caused by the propagation delay of the signals on the shared bus from the first device under test (DUT 1 ) to the second device under test (DUT 2 ).
  • fixture delay of the first device it is not obligatory to use the fixture delay of the first device.
  • fixture delay of the second, third or N-th device could be used as well.
  • FIG. 3 shows a block schematic diagram of a chip tester connected to two devices under test.
  • the chip tester in FIG. 3 is designated in its entirety with 300 .
  • the chip tester 300 is similar to the chip tester 100 of the FIG. 1 .
  • same means and signals are designated with the same reference numerals and will not be explained here again. Instead, reference is taken to the description of the FIG. 1 .
  • the chip tester 300 also comprises a third channel 138 .
  • a third channel port 139 is associated with the third channel 138 .
  • the second channel port 136 is in an embodiment connected with a second terminal 154 of the first dut 150 .
  • the third channel port 139 is connected with a second terminal 164 of the second dut 160 .
  • the first dut 150 is of the same type as the second dut 160 .
  • the first dut 150 and the second dut 160 may, for example, be two samples out of a set of chips which are assumed to be identical under ideal circumstances.
  • the second channel 132 and the third channel 138 may either both be input channels or may both be output channels.
  • the definition “output channel” comprises an input/output channel configured (e.g. by means of software or by means of a hardware switch) to act as an output port.
  • the term “input channel” comprises an input/output channel configured to act as an input port.
  • a propagation delay between a first channel port 134 and the first terminal 152 of the first dut 150 is designated with ⁇ tp 1 .
  • a propagation delay between the first channel port 134 and a first terminal 162 of the second dut 160 is designated with ⁇ tp 2 .
  • a propagation delay between a second channel port 136 and the second terminal 154 of the first duty 150 is designated ⁇ t 2 .
  • a propagation delay between the third channel port 139 and the second terminal 164 of the second dut 160 is designated ⁇ t 3 .
  • the second dut terminal 154 of the first dut 150 and the second terminal 164 of the second dut 160 are input terminals.
  • the duts 150 , 160 may also comprise output terminals, but the output terminals are not shown here for the sake of simplicity. Consequently, it is assumed that the second channel 132 and the third channel 138 are driver channels.
  • the propagation delays ⁇ tp 1 , ⁇ tp 2 , ⁇ t 2 , ⁇ t 3 are known to the chip tester.
  • the chip tester may be adapted to read a file comprising said propagation delay values.
  • the chip tester may, for example be adapted to perform a time domain reflection (TDR) measurement in order to determine said propagation delay values.
  • TDR time domain reflection
  • the chip tester is adapted to primarily obtain a propagation delay difference information 112 .
  • the propagation delay difference information 112 describes the difference between the propagation delay ⁇ tp 2 and propagation delay ⁇ tp 1 . Consequently, the timing calculator 110 calculates the timing information 114 defining the relative timing of the second channel 132 and the third channel 138 . A time shift between the timing of the second channel 132 and the third channel 138 is adjusted in dependency on the propagation delay difference information 112 .
  • a relative time shift between the signal outputs of the second channel 132 and the third channel 138 is adjusted by taking into consideration the propagation delay difference information, i.e. the difference ⁇ tp 2 ⁇ tp 1 .
  • the timing calculator 110 may in an alternative embodiment consider further information, for example, the propagation delay values ⁇ t 2 and ⁇ t 3 , when calculating timing information 140 for a relative timing of the second channel 132 and the third channel 138 .
  • the propagation delay values ⁇ t 2 and ⁇ t 3 may be neglected for the determination of a relative timing between the second channel and the third channel if said propagation delay values are approximately identical, which may, for example, be reached by an appropriate routing of the non-shared connections for the second terminal 154 of the first dut 150 and the second terminal 164 of the second dut 160 .
  • the timing calculator 110 may optionally (but not necessarily) be adapted to calculate a timing information for the first channel 130 . By providing the timing information for the channels 130 , 132 , 138 , a specific relative timing of the different input signals to the first dut 150 and the second dut 160 can be adjusted.
  • FIGS. 4 a , 4 b and 4 c describe a setting of timings, which may be used in an embodiment of the invention.
  • this is naturally an arbitrary choice, and a different time reference could be chosen.
  • the signal form the shared driver 130 arrives at the second dut 160 later by a propagation delay difference ( ⁇ tp 2 ⁇ tp 1 ) than it arrives at the first dut 150 .
  • FIG. 4 c shows the signals provided by the third channel 138 .
  • a time difference between the signal provided by the first channel 130 at the first channel port 134 and the signal provided by the second channel 132 at the second channel port 136 is ⁇ t 2 + ⁇ tp 1.
  • a time difference between the signal provided by the third channel 138 at the third channel port 139 and the signal provided by the second channel 132 at the second channel port 136 is ⁇ (( ⁇ tp 2 + ⁇ tp 1)+ ⁇ t 3 ⁇ t 2).
  • FIGS. 4 d , 4 e and 4 f describe another advantageous setting of the timings. It should be noted here that in order to provide a sufficient synchronism of the input signals of the first dut 150 and the second dut 160 , it is sufficient for the timing calculator to know the propagation delay difference information 112 , i.e. ⁇ tp 2 ⁇ tp 1 . In a basic embodiment, the timing calculator 112 can then provide timing information 114 , which directs the channel module configurator 120 to introduce a time shift identical to the propagation delay difference information between the timings of the third channel 138 and the second channel 132 .
  • the timing calculator 110 provides timing information to the channel module configurator 120 which results in a timing configuration of the third channel 138 and the second channel 132 , such that the third channel 138 provides the same signal pattern as the second channel 132 , wherein the signal pattern provided by the third channel 138 is delayed with respect to the signal pattern provided by the second channel 132 by ( ⁇ tp 2 ⁇ tp 1 ).
  • This case is illustrated in FIG. 4 d .
  • the timing calculator 112 may provide the timing information 114 taking into consideration ⁇ t 2 and ⁇ t 3 . In this case, a time shift between the signal patterns provided by the second channel 132 and the third channel 138 is adjusted to ⁇ tp 2 ⁇ tp 1 + ⁇ t 2 ⁇ t 3.
  • the timing calculator 110 may additionally be adapted to provide the timing information to set a timing relationship between the first channel 130 and the second channel 132 .
  • the timing calculator receives an information about the propagation delay ⁇ tp 1 and the propagation delay ⁇ t 2 .
  • the timing calculator receives an information about the propagation delay difference information ⁇ tp 2 ⁇ tp 1 (and, optionally, a propagation delay time information ⁇ t 2 ⁇ t 3 ) the timing of the second channel 132 and the third channel 138 can be adjusted such that both duts 150 and 160 receive corresponding signals with the same timing relationship.
  • the timing calculator 110 is adapted to receive the propagation delay difference information ⁇ tp 2 ⁇ tp 1 , the propagation delay information ⁇ tp 1 , the propagation delay information ⁇ t 2 and either information about ⁇ t 2 ⁇ t 3 or the information ⁇ t 3 itself. Based on this information, the timing calculator 110 is adapted to set the timings of the three channels 130 , 132 , 138 as shown in FIG. 4 d . In other words, the timing calculator is adapted to provide timing information to delay the second channel 132 by ⁇ tp 1 ⁇ t 2 with respect to the first channel 130 .
  • the timing calculator 110 is adapted to provide timing information 114 to adjust a timing of the third channel 138 and the second channel 132 , such that the timing of the third channel is delayed with respect to the timing of the second channel by ⁇ tp 2 ⁇ tp 1 , or by ⁇ tp 2 ⁇ tp 1 + ⁇ t 2 ⁇ t 3 .
  • Such a setting of the timings of the channels 130 , 132 , 138 has the effect that the wave forms output by the first channel and the second channel arrive simultaneously at the first dut 150 and that the wave forms output by the first channel and the third channel arrive simultaneously at the second dut 160 .
  • the graphical representation of FIG. 4 d describes the wave forms output by the first channel 130 , the second channel 132 and the third channel 138 as a function of time.
  • An abscissa 410 describes a time and ordinates 412 , 414 , 416 describe the respective signals in terms of arbitrary units. Timing shifts between the output signals of the first channel 130 , the second channel 132 and the third channel 138 are also shown in the graphical representation of FIG. 4 d.
  • FIG. 4 e shows a graphical representation of wave forms arriving at the first device under test 150 in response to the output wave forms of the first channel 130 , the second channel 132 and the third channel 138 shown in FIG. 4 d.
  • An abscissa 420 describes the time and ordinates 422 , 424 describe the signals present at the input terminals 152 , 154 of the first dut 150 in terms of arbitrary units.
  • the corresponding signals arrive at the input terminals 152 , 154 of the first dut 150 simultaneously.
  • the signals at the input terminals 152 , 154 of the first dut 150 are in a specific relative timing relationship (here: simultaneous arrival).
  • An abscissa 430 describes the time and ordinates 432 , 434 describe the signals at the input terminals 162 , 164 at the second dut 160 . It should be noted here that for the timing of the first channel 130 and the third channel 138 shown in FIG. 4 d , the signals at the input terminals 162 , 164 of the second dut 160 arrive simultaneously. In other words, the signals arriving at the input terminals 162 , 164 are in a specific relative timing relationship (here: simultaneous arrival).
  • Adjusting the relative timing of two channels, one of which provides and unshared signal to the first dut 150 and one of which provides and unshared signal to an input terminal of the second dut 160 taking into account the propagation delay difference information about a difference of propagation delays on a shared line connected to both duts 150 , 160 allows for an elimination of the impact of the propagation delay difference on the shared line. Consequently, a relative signal timing present at the first dut 150 is identical to a relative signal timing of signals present at the second dut 160 .
  • both duts 150 , 160 are tested under identical (relative) timing conditions. For this reason, identical test results can be expected for the first dut 150 and the second dut 160 , provided the duts 150 , 160 are identical.
  • an embodiment of the present invention allows a quasi-simultaneous (i.e. almost simultaneous but shifted by ⁇ tp 2 ⁇ tp 1 ) testing of two devices making use of both shared inputs and unshared inputs or unshared outputs. Even high speed devices can be tested making use of the inventive concept, according to an embodiment of the present invention.
  • the second terminal 154 of the first dut 150 is an output terminal and that the second terminal 164 of the second dut 160 is also an output terminal.
  • the timing of the second channel 132 and of the third channel 138 are adjusted by the channel module configurator 120 in response to the timing information 140 provided by the timing calculator 110 .
  • the timing of the third channel 138 is delayed with respect to a timing of the second channel 132 by ⁇ tp 2 ⁇ tp 1 .
  • the timing of the third channel 138 is delayed with respect to the timing of the second channel 132 by ⁇ tp 2 ⁇ tp 1 + ⁇ t 3 ⁇ t 2 .
  • the timing of the third channel 138 is delayed with respect to the timing of the second channel on the basis of the propagation delay difference information.
  • An example timing of a corresponding chip test set up is shown in FIG.
  • FIG. 5 shows a graphical representation of signals and timings which may be present in the chip tester 300 of FIG. 3 according to an embodiment of the present invention.
  • the first channel 130 provides a signal wherein a signal transition arrives at the first channel port 134 at time t 1 .
  • the signal transition arrives at the first dut 150 at time t 1 + ⁇ tp 1 and at the second dut at time t 1 + ⁇ tp 2 .
  • the second channel 132 is adapted to sample an output signal of the first dut 150 at time t 1 + ⁇ tp 1 + ⁇ t 2 +tD.
  • the third channel 138 is configured to sample a signal provided by the second dut 160 at the time t 1 + ⁇ tp 2 + ⁇ t 3 +tD. It should be noted here that the timing shift between the second channel 132 and the third channel 138 has been configured by the timing calculator 110 and the channel module configurator 120 on the basis of the propagation delay difference information 112 .
  • the second channel effectively determines a signal, which is present at the output 154 of the first dut 150 when a time tD has elapsed after the transition of the input signal of the first dut 150 .
  • the third channel 138 evaluates a signal which is present at the output 164 of the second dut 160 when a time tD has elapsed after a transition of the input signal of the second dut 160 .
  • the above described shift of the timings of the second channel 132 and the third channel 138 has the effect that corresponding output signals of the duts 150 , 160 are sampled, occurring at identical relative timing positions with respect to the respective input signals of the duts 150 , 160 .
  • the above described configuration of the second channel 132 and the third channel 138 has the effect that identical duts 150 , 160 produce identical test results despite the propagation delay difference ⁇ tp 2 ⁇ tp 1 , even in a high speed test environment.
  • Fixture delay calibration is a dedicated tool to compensate delays along a signal path of an interface or a dut board (e.g. between a channel port of a tester channel and a dut terminal, or between a channel port of a tester channel and a dut connection element for connection of a dut). For this reason, an embodiment of the present invention comprises a concept (i.e. a method or an apparatus) that is based on the fixture delay calibration.
  • the fixture delay calibration can still be used to compensate the propagation delay caused by the dut interface, even when driver sharing is implemented.
  • it is only needed that the fixture delay values measured are modified to ensure synchronism for all duts. This can be achieved by an additional tool performing a post-processing on the fixture delay calibration files.
  • the chip tester is adapted to obtain information about a propagation delay between the channel port of the tester and a terminal of a dut. If the chip tester obtains the information that there is a certain delay between a certain channel port and a certain dut terminal, the chip tester configures the timing of the respective chip tester channel accordingly. If the chip tester channel is an output channel, the chip tester will advance the timing of the respective channel with respect to a reference timing in order to compensate for the propagation delay. If the channel is an input channel, the chip tester will delay the timing of the input channel with respect to a reference timing in order to compensate for the propagation delay. It should be noted here that the reference timing may, for example, be a timing under the assumption that there is no delay present between the channel port and the dut terminal.
  • a fixture delay measurement is performed using a short circuit device inserted into a dut socket (or dut connection element) instead of an actual device.
  • a time domain reflection measurement is made by providing an excitation signal to a chip tester port (or chip tester connection element) of the dut board and by measuring a response signal at the dut port (or dut connection element).
  • the first reason is the fact that the DQ lines (or shared lines, or data lines) are configured as dual transmission lines and that the location of the dut terminal (or dut pin or dut connection element) can only be identified with a short at that point.
  • the second reason is the fact that the shared bus also behaves like a dual transmission line when we look at it from the perspective of one dut.
  • the measurements are repeated, placing a short circuit device into the different dut sockets subsequently, until a measurement of a N-th dut (DUT N) is stored in a N-th file (file N).
  • the different fixture delay calibration files represent different delays for the shared inputs depending on which dut socket was loaded with the short circuit device plus the delays of the unshared inputs and the outputs that belong to the same dut.
  • a way to compensate the different signal paths for the individual duts on the shared bus in a single fixture delay file is as follows:
  • N fixture delay calibration files (or in any other appropriate data structure), wherein N is the sharing factor.
  • these files are supplied from the interface manufacturer who performs this measurement after manufacturing (the interface or the dut board) using time domain reflection (TDR) equipment.
  • TDR time domain reflection
  • the N fixture delay calibration files can also be generated with a fixture delay calibration tool contained in the “SmarTest” software provided by the applicant.
  • the next step is to compensate the signal path to the first dut in a conventional way, leaving the fixture delay data of the first dut (DUT 1 ) untouched.
  • the third step is to compensate the signal path to the other duts on the shared bus (DUT 2 . . . DUT N) by modifying the fixture delay values of the unshared inputs and the outputs.
  • the signals of the unshared inputs of DUT 2 have to be delayed by the same amount ⁇ t 12 . Since all input signals are now delayed by the same amount relative to the arrival of the signal at DUT 1 , the output of DUT 2 will also be delayed by the same amount ⁇ t 12 . Therefore, the compare action taking place in the receiver channels has to be delayed accordingly.
  • the delay ⁇ t 12 is achieved on the unshared inputs and the outputs of DUT 2 , a synchronism will also be guaranteed for DUT 2 , and the device can be tested as usual.
  • the delay of the unshared input signals and the output signals can be achieved by the modification of the respective fixture delay calibration values of each dut. This is possible because, in contrast to the shared inputs, the unshared inputs and the outputs of each dut are connected to individual tester channels.
  • the measured fixture delay values of the unshared inputs and the outputs are modified to account for the additional delay ⁇ t 12 , relative to the first dut ( ⁇ t 12 , ⁇ t 13 . . . ⁇ t 1 N if there are N devices on one shared bus).
  • the respective fixture delay values In order to delay the signals on the unshared inputs by the amount of ⁇ t 12 , the respective fixture delay values have to be reduced by ⁇ t 12 .
  • the reduced fixture delay values have the consequence that the tester drivers send their stimulus signals later, assuming that the shorter signal path has to be compensated.
  • the respective fixture delay values In order to delay the signals on the dut outputs, the respective fixture delay values have to be increased by ⁇ t 12 .
  • the increased fixture delay values have the consequence that the tester receivers perform their compare action later, assuming a longer signal path has to be compensated.
  • the above described post-processing first analyses the N fixture delay calibration files (or any other data structure, in which the respective propagation delay values are provided) and calculates the difference (or propagation delay difference) between the second dut (DUT 2 ) and the first dut (DUT 1 ) for each shared input.
  • the delay ⁇ t 12 is obtained by averaging the differences on all shared inputs. Because of the averaging, in an embodiment of the present invention the lengths of the shared bus between the second dut (DUT 2 ) and the first dut (DUT 1 ) are precisely length matched.
  • the post-processing subtracts the value ⁇ t 12 from the fixture delay value of each unshared input of the second device (DUT 2 ).
  • the post-processing finally combines the new and unchanged fixture delay values for all duts and stores it into a new fixture delay calibration file (or provides any other appropriate data structure). If there are N devices on the shared bus, the procedure is applied for all duts from the second dut (DUT 2 ) to the N-th dut (DUT N) (i.e. the procedure is applied to DUT 2 , DUT 3 , . . . DUT N), processing the respective delays ⁇ t 12 , ⁇ t 13 , . . . ⁇ t 1 N in the same way for each dut.
  • the values measured for the unshared inputs during fixture delay calibration are dominated by the propagation delay of a cable connecting a socket board (or dut board) with the motherboard.
  • these values are reduced during post-processing to account for the delay between the first dut (DUT 1 ) and the N-th dut (DUT N) on the shared bus, the result is typically positive, since the delays on the cables are typically larger than the delays on the traces of the shared board.
  • the delay on the shared bus may exceed the delay on the cable and a negative value may be the result of the post-processing.
  • an additional offset can optionally be added to the fixture delay values of all inputs and subtracted from the fixture delay values of all outputs before applying the above modification procedure.
  • a conventional fixture delay calibration and the above described post-processing sequence can be performed for the K buses in parallel using K short circuit devices.
  • N fixture delay calibration files are generated containing the measurement data of all K buses.
  • any other appropriate data structure may be generated.
  • ⁇ t 12 for all K buses is processed in a first step, followed by ⁇ t 13 . . . ⁇ tN.
  • the result of the post-processing is one new fixture delay calibration file, valid for a whole interface (or for a whole dut board).
  • any other appropriate data structure may be created.
  • FIG. 6 shows a block schematic diagram of an apparatus for post-processing an original propagation delay value, according to an embodiment of the present invention.
  • the apparatus of FIG. 6 is designated in its entirety with 600 .
  • the apparatus 600 is adapted to post-process a plurality of propagation delay values of a dut interface (or dut board) for a chip tester.
  • the dut interface (or dut board) is adapted to provide an electrical connection between a chip tester and at least two duts
  • the dut board comprises a first dut contact element for providing a detachable electrical contact between the dut board and a first dut, a second dut contact element for providing a detachable electrical contact between the dut board and the second dut, a third dut contact element for providing a detachable electrical contact between the dut board and the first dut and a fourth dut contact element for providing a detachable electrical connection between the dut board the second dut.
  • the dut board comprises a first chip tester contact element for providing a detachable electrical contact between the dut board and a chip tester.
  • the dut board comprises a second chip tester contact element for providing a detachable electrical contact between the dut board and the chip tester, and a third chip tester contact element for providing a detachable electrical contact between the dut board and the chip tester.
  • the first dut contact element and the second dut contact element are both electrically connected to the first chip tester contact element.
  • the third dut contact element is electrically connected to the second chip tester contact element, and the fourth dut contact element is electrically connected to the third chip tester contact element. Details regarding a possible dut interface configuration are shown in FIGS. 7 a to 7 c.
  • dut board is described as an example of a dut interface.
  • other types of dut interfaces for providing a connection between the chip tester and one or more duts can be used.
  • the apparatus 600 comprises a propagation delay determinator 610 , which is adapted to obtain an original (or actual) propagation delay value describing a propagation delay between the fourth dut contact element and the third chip tester contact element.
  • the propagation delay determinator 610 is adapted to provide the obtained propagation delay value as an original propagation delay value 612 .
  • the apparatus 600 comprises a propagation delay difference value determinator 620 , which is adapted to obtain and provide a propagation delay difference 622 , describing a difference between, on the one hand, a propagation delay between the first chip tester contact element and the first dut contact element, and, on the other hand, a propagation delay between the first chip tester contact element and the second dut contact element.
  • the apparatus 600 comprises a propagation delay modifier 630 , which is adapted to modify the original propagation delay value 612 using the propagation delay difference value 622 . Consequently, the propagation delay modifier 630 is adapted to provide a modified effective propogation delay value 632 .
  • the modified effective propagation delay value 622 may take the place of the original propagation value 612 .
  • the modified effective propagation delay value 622 may, for example, be used as the timing information 140 , which serves as an input information for the channel module configurator 120 in the chip tester 100 . It should also be noted that the apparatus 600 can be considered to make up the timing calculator 110 of the chip tester 100 .
  • the apparatus 600 is adapted to produce a data structure (for example, a file) on the basis of one or more modified effective propagation delay values 632 .
  • the apparatus 600 may, in an embodiment, be adapted to process as an input information one or more of the above-described fixture delay calibration files and to produce a new fixture delay calibration file (which may also be designated as a modified fixture delay calibration file, or an effective fixture delay calibration file) on the basis of one or more of the modified effective propagation delay values.
  • FIG. 7 a shows an example of a dut board for a driver sharing test of at least two duts.
  • the dut board of FIG. 7 a is designated in its entirety with 700 .
  • FIG. 7 a shows graphical representations of two possible dut board propagation delay data structures, which are designated with 720 and 730 .
  • the dut board 700 comprises 3 chip tester contact elements 702 , 704 , 706 .
  • the chip tester contact elements are adapted to provide an electrical connection between the chip tester and the dut board 700 .
  • the chip tester contact elements may, for example, be contact elements, which are adapted to interact with a POGO interface of a chip tester.
  • the dut board 700 comprises 4 dut contact elements 710 , 711 , 712 , 713 .
  • the dut contact elements are adapted to provide an electrical contact between the dut board 700 and two duts.
  • first dut contact element 710 and the third dut contact element 712 are adapted to provide electrical contacts with two different terminals of a first dut
  • second dut contact element 711 and the fourth dut contact element 713 are adapted to provide an electrical contact to two different terminals of a second dut.
  • the first and third dut contact elements 710 , 712 may, for example, be a part of a first dut socket for the first dut, and the second and fourth dut contact elements 711 , 713 may, for example, be part of a second dut socket for a second dut.
  • first and second dut contact elements 710 , 711 are electrically connected to the first chip tester contact element 702 via a shared line.
  • first dut contact element 710 and the second dut contact element 711 are both connected to the same chip tester contact element. The connection is performed by a transmission line on the dut board.
  • the third dut contact element 712 is electrically connected to the second chip tester contact element 704
  • the fourth dut contact element 713 is electrically connected to the third chip tester contact element 706 .
  • an original data structure (e.g. an original file) exists, which describes physical characteristics of the dut board 700 .
  • the data structure may comprise the information as shown for the file 720 .
  • the original data structure or file may comprise an information about a propagation delay between the first chip tester contact element 702 and the first dut contact element 710 , which is designated with ⁇ tp 1 .
  • the original data structure may comprise information about a propagation delay between the first chip tester contact element 702 and the second dut contact element 711 , which is designated with ⁇ tp 2 .
  • the original data structure may further comprise information about a propagation delay between the third dut contact element 712 and the second chip tester contact element 704 designated with ⁇ t 2 , and an information about a propagation delay between the fourth dut contact element 713 and the third chip tester contact element 706 designated with ⁇ t 3 .
  • the information regarding the first dut namely ⁇ tp 1 , ⁇ t 2
  • the information regarding the second dut namely ⁇ tp 2 , ⁇ t 3
  • a modified data structure comprising modified (or effective) propagation delay values is provided with the dut board.
  • the dut board and the modified data structure may be considered to be a dut board set or test fixture set.
  • the modified data structure (or modified file) comprises an information about the propagation delay between the first chip tester contact element 702 and the first dut contact element 710 , for example, the value ⁇ tp 1 .
  • the modified data structure comprises an information about the propagation delay between the third dut contact elements 712 and the second chip tester contact element 704 , for example, the value ⁇ t 2 .
  • the modified data structure comprises a modified (or effective) information about a propagation delay between the forth dut contact elements 713 and the third chip tester contact element 706 .
  • Said amended or effective propagation delay value is, in an embodiment of the present invention, based on the actual propagation delay value ⁇ t 3 and amended on the basis of a propagation delay difference information describing a difference of propagation delays between, on the one hand, the first chip tester contact element 702 and the first dut contact element 710 and, on the other hand, the first chip tester contact element 702 and the second dut contact element 711 .
  • the modified propagation delay value may be computed as ⁇ t 3 ⁇ ( ⁇ tp 2 ⁇ tp 1).
  • the original propagation delay values between the third dut contact element and the second chip tester contact element ( ⁇ t 2 ), and between the fourth dut contact element and the third chip tester contact element ( ⁇ t 3 ) are modified in such a way that a difference between the amended (or effective) propagation delay values ( ⁇ t 3 ,effective ⁇ t 2 ,effective) deviates from a difference between the original propagation values ( ⁇ t 3 ⁇ t 2 ) by the propagation delay difference for the shared line ( ⁇ tp 2 ⁇ tp 1 ).
  • the amended or effective propagation delay values may be comprised in one or more data structures. Exemplary data structures are shown in FIG. 7 b , describing an effective dut board 740 .
  • an amended data structure (or effective data structure) may, for example, comprise the propagation delay value ⁇ tp 1 , the propagation delay value ⁇ t 2 ,effective and the propagation delay value ⁇ t 3 ,effective.
  • two data structures or two separate files may be provided, a first file comprising the propagation delay values ⁇ tp 1 and ⁇ tp 2 ,effective and the second file comprising the propagation delay values ⁇ tp 1 and ⁇ t 3 ,effective.
  • the amended propagation delay data structures described with reference to FIG. 7 b may, for example, be applied if the dut contact element 712 , 713 are intended to be connected to input ports of a dut.
  • FIG. 7 c shows a graphical representation of an effective dut board and of a corresponding data structures characterizing the effective dut board.
  • the effective propagation delay ⁇ t 3 effective between the third chip tester contact element and the fourth dut contact element is chosen to be ⁇ t 3+( ⁇ tp 2 ⁇ tp 1)
  • the data structure described with reference to FIG. 7 c may, for example, be used if the third dut contact element and the fourth dut contact element are intended to be connected to output ports of two duts.
  • FIG. 7 d shows an example of an extended configuration for testing two duts.
  • the configuration of FIG. 7 d comprises a first dut 790 and a second dut 792 .
  • An input 790 a of the first dut 790 and an input 792 a of the second dut 792 may be configured to be shared inputs. Said inputs 790 a , 792 a of the first and second dut 790 , 792 may therefore be connected to a shared output of the chip tester.
  • the first dut 790 may comprise at least one unshared input 790 b and at least one unshared output 790 c .
  • the second dut 792 may also comprise at least on unshared input 792 b and at least one unshared output 792 c.
  • a device has shared inputs, unshared inputs and unshared outputs.
  • FIG. 8 shows a block schematic diagram of a test environment comprising at least two duts, each of which comprises at least two shared inputs.
  • the test environment of FIG. 8 is designated in its entirety with 800 .
  • a first dut is designated with 810 and a second dut is designated with 820 .
  • the first dut 810 comprises a first shared input 812 and a second shared input 814 .
  • the first dut 812 comprises an additional input or output 816 .
  • the second dut 820 comprises a corresponding first shared input 822 , a second shared input 824 and another input or output 826 .
  • the first shared input 812 of the first dut and the first shared input 822 of the second dut are both connected to a shared, bus-like transmission line 830 .
  • the second shared input 814 of the first dut and the second shared input 824 of the second dut are both connected to a second shared, bus-like transmission line 832 .
  • the first shared transmission line 830 comprises a chip tester contact element 834
  • the second shared transmission line 832 comprises a corresponding chip tester contact element 836 .
  • the propagation delay between the chip tester contact element 834 and the first shared input 812 is designated with ⁇ tp 1 , 1 .
  • the propagation delay between the chip tester contact element 834 and the first shared input 822 of the second dut is designated with ⁇ tp 1 , 2 .
  • the propagation delay between the chip tester contact element 836 and the second shared input 814 is designated with ⁇ tp 2 , 1 and a propagation delay between the second chip tester contact element 836 and the second shared input 824 is designated with ⁇ tp 2 , 2 . Consequently, the propagation delay difference value ⁇ tp 1 , 2 ⁇ tp 1 , 1 for the first shared transmission line can be determined.
  • a propagation delay difference value ⁇ tp 2 , 2 ⁇ tp 2 , 1 for the second shared transmission line can be determined.
  • an average value can be used, which can be obtained by averaging the propagation delay difference values for individual transmission lines.
  • FIG. 9 shows a graphical representation of a test fixture set, according to an embodiment of the present invention.
  • the test fixture set is designated in its entirety with 900 .
  • the text fixture set 900 comprises a dut board 910 , which may be identical to the dut board 700 , described with reference to FIG. 7 a . For this reason, reference is taken to the above description.
  • the test fixture set 900 further comprises a data exchange medium or data carrier 920 comprising the amended (or effective) propagation delay information, as described, for example, with reference to FIGS. 7 b and 7 c .
  • the data exchange medium or data carrier 920 may represent one or more of the data structures or files described with reference to FIGS. 7 b and 7 c .
  • the data exchange medium or data carrier may comprise an amended or effective propagation delay value for at least one of the transmission lines of the dut board 910 .
  • the data exchange medium or data carrier 920 corresponds to the dut board 910 .
  • the data exchange medium 920 does not, or does not only, comprise actual or physical information about the propagation delays of the transmission lines of the dut board 910 , but also (or exclusively) comprises amended (or effective) propagation delay values, the generation of which was, for example, described with reference to FIGS. 7 b and 7 c.
  • the data exchange medium 920 may, for example, be a harddisk, floppy disc, a CD ROM, a DVD, a ROM, a PROM, a EPROM, a EEPROM or a /memory comprising said amended propagation delay values.
  • the data exchange medium or data carrier may also be any other volatile or non-volatile data carrier comprising said amended propagation delay values.
  • a data packet adapted to be transported via a data transport network is also considered to be a data carrier or a data exchange medium.
  • the test fixture set may also take the form of a physical dut board and an online transmission of the corresponding amended propagation delay values.
  • FIG. 10 shows a test setup comprising 4 duts.
  • FIG. 10 shows a block schematic diagram of a test set up comprising 4 duts.
  • FIG. 10 shows propagation delays on a shared bus for a by ⁇ 4 sharing.
  • the test set up in FIG. 10 is designated in its entirety with 1000 .
  • the test set up 1000 comprises 4 duts 1010 , 1012 , 1014 , 1016 .
  • Each of the duts comprises, for example, three shared inputs designated with 1010 a , 1010 b , 1010 c , 1012 a , 1012 b , 1012 c , 1014 a , 1014 b , 1014 c , 1016 a , 1016 b , 1016 c .
  • Shared inputs 1010 a , 1012 a , 1014 a , 1016 a are all connected to a first shared line 1020 a , which is driven by a first channel 1022 a of a chip tester.
  • Shared inputs 1010 b , 1012 b , 1014 b , 1016 b are all connected to a shared line 1020 b , which is driven by a second channel 1022 b of the chip tester.
  • Shared inputs 1010 c , 1012 c , 1014 c , 1016 c are all connected to a third shared line 1020 c , which is driven by a third channel 1022 c of the chip tester.
  • the shared transmission lines 1020 a , 1020 b , 1020 c are (optionally) terminated by transmission line terminations 1024 a , 1024 b , 1024 c.
  • the shared transmission lines are length-matched in an embodiment of the invention.
  • the shared transmission lines comprise branch points (e.g. branch points 1030 a , 1030 b , 1030 c ), at which individual dut transmission lines branch from the shared transmission lines.
  • branch points e.g. branch points 1030 a , 1030 b , 1030 c
  • the length of the shared transmission lines between corresponding branch points are (at least approximately) identical.
  • a length of a segment of the first transmission line 1020 a between the branch point 1030 a and the branch point 1032 a is, at least approximately, identical to the length of a segment of the second transmission line 1020 b between the branch point 1030 b and the branch point 1032 b .
  • a propagation delay between the branch point 1030 a and the branch point 1032 a is, at least approximately, identical to a propagation delay between the branch point 1030 b and the branch point 1032 b , and also identical to the propagation delay between the branch points 1030 c and 1032 c .
  • the length L 23 may be different from the length L 12 .
  • the length L 34 my be different from the length L 23 .
  • lengths L 12 , L 23 and L 34 may be at least approximately identical.
  • duts e.g. memory devices
  • a fixture delay calibration that just compensates the propagation delays of the signal paths including the shared bus as described above
  • the timing related results of some measurements for example, the set up and hold times
  • different measurement results are obtained when some dut sockets on the shared bus are not loaded with devices.
  • the reason for this dependency is that the delay of the signals on the shared bus is not only caused by the limited propagation velocity on the socket board traces (or dut board traces), but also by a parasitic load of duts connected to the shared bus.
  • the loading is dominated by an input capacitance of the shared inputs and causes a distortion of the signals that includes certain delays of the signal transitions.
  • the device loading effect may be taken into account.
  • An influence of the device loading on the total signal delay on the shared bus can, for example, be included into the fixture delay calibration.
  • the fixture delay calibration can be performed with a short circuit device inserted in one dut socket and the dut sockets preceeding the shorted circuit loaded with regular devices. Performing a fixture delay calibration with devices loaded up to the short circuit device yields a second set of N fixture delay calibration files with significantly larger values for the shared inputs of DUT 2 , . . . DUT N.
  • the values measured with devices may be subtracted from the values measured without devices.
  • the additional load is caused by DUT 1 only, whereas for DUT N, the additional load is caused by DUT 1 , . . . DUT (N ⁇ 1).
  • the loading effect increases from DUT 2 to DUT N for each additional dut.
  • DUT 1 shows the same results with and without devices, because there are no preceding devices (i.e. devices located closer to the chip tester channel than DUT 1 ) to the dut measured. This allows a simplification of the extraction procedure for the loading effect per dut. It is sufficient that only the fixture delay measurement for DUT N is performed with devices loaded into the circuits of DUT 1 to DUT (N ⁇ 1).
  • the fixture delay values for DUT 1 (e.g. ⁇ tp 1 ) can be taken from the measurement without devices because there is no difference. It is also sufficient to determine a loading effect per dut from only one shared bus (or from one socket board or dut board).
  • the value t L for the loading effect can be obtained from a simulation, or from some other calculation.
  • FIG. 11 shows a flow chart of an inventive method for performing measurements in preparation of a device load compensation.
  • the method of FIG. 11 is designated in its entirety with 1100 .
  • a first step 1110 comprises determining a propagation delay ⁇ tp 1 for a first dut (i.e. a propagation delay between a chip tester contact element of the dut board a dut contact element of the dut board for the first dut).
  • a propagation delay ⁇ tp 1 for a first dut i.e. a propagation delay between a chip tester contact element of the dut board a dut contact element of the dut board for the first dut.
  • the numbering of the duts (1st dut, 2nd dut, . . . ) is chosen such that a lower number of dut indicates that the propagation delay between the chip tester contact element of the dut board and the dut, or between the chip tester channel and the dut, is smaller.
  • an unloaded propagation delay for a second dut (with index n>1) is determined.
  • a dut socket for the first dut is left open, and a short circuit element is placed in the dut socket of the second dut. Consequently, the propagation delay ⁇ tp 2 is measured, for example, by performing a time domain reflection measurement.
  • a third step 1114 an unloaded propagation delay for the third dut is determined.
  • a dut socket of the first dut and the second dut are left open, and a short circuit element is placed in the dut socket for the third dut. Consequently, the propagation delay ⁇ tp 3 is measured, for example, by making a time domain reflection measurement.
  • the measurement can optionally be extended to cover more than three duts.
  • the order, in which the first step 1110 , the second step 1112 and the third step 1114 are executed can be chosen arbitrarily. However, it should also be noted that the first step 1110 , the second step 1112 and the third step 1114 can already be performed before a dut is available, and even before it is known which load an actual dut presents to the shared lines. It should also be noted that according to one embodiment of the present invention, the steps 1110 , 1112 , 1114 are executed by the manufacturer of a dut board.
  • a propagation delay value is determined in a loaded state of the dut board.
  • a dut or an equivalent load device which presents a load to the shared lines that is approximately identical to the load presented by the dut, is placed in at least one dut socket.
  • a short circuit device is placed in a higher number dut socket.
  • all the sockets between the chip tester contact element and the dut socket with the short circuit device are loaded with duts or load devices, but this is not obligatory. Rather, it is sufficient if at least one dut or load device is used.
  • the propagation delay ⁇ t 13 in a loaded state can be determined by, for example, making a time domain reflection measurement.
  • a propagation delay contribution per dut can, for example, be obtained by comparing results of propagation delay measurements for the same dut position in an unloaded state and in a loaded state of other dut positions, taking into consideration how many duts or loaded devices have been effective in said measurements.
  • the propagation delay measurement in a loaded state only needs to be made for one single load situation to determine a propagation delay contribution per dut.
  • Loaded state propagation delays for other load situations can then be calculated by means of interpolating or extrapolating, assuming that each dut increases linearly a propagation delay.
  • propagation delays for various load states can be calculated. For example, a propagation delay can be calculated for a situation where the first dut and the third dut are placed on a dut board, but wherein a second dut socket is left open. Accordingly, different load states can consequently be handled without taking a measurement for each single load state.
  • a propagation delay can be calculated for a load situation, in which at least one dut socket is unloaded, based on the assumption that each loaded dut socket contributes a certain pre-determined propagation delay, and further based on the assumption that an unloaded dut socket does not provide a contribution to the propagation delay.
  • a reconfiguration of the timing of the chip tester channels may be performed in response to a change of a loading state of the dut sockets. For example, during a test of a plurality of duts in a multi-socket arrangement with shared lines, it may be found that a specific dut socket brings along a particularly high failure rate. In this case, it may, for example, be assumed that the specific socket is defective. Therefore, it may be decided not to place any more duts in the specific dut socket. Accordingly, after the decision not to load the specific dut socket with duts, subsequent testing is performed in a load configuration wherein at least one of the dut sockets is unloaded.
  • a timing of the chip tester channels or at least of one chip tester channel may be recomputed in response to the decision to change a loading state of a specific dut socket.
  • the change of the timing of the chip tester channel is performed such as to compensate for the timing change due to the change of the load state.
  • a common strategy of semiconductor manufacturers who perform multi-site testing is the disabling of sites that permanently fail. If a site is disabled, it will no longer be loaded from a device handler and, thus, does no longer show a loading effect. The consequence of this strategy is that the calculation of the ⁇ t 1i [with devices] should take care of disabled sites. The handler communicates the disabling of sites to the tester, therefore, this information is available. However, since this information is created dynamically during run time of the test, whereas the fixture delay calibration data are loaded statically at the beginning of a test flow, the test may have to be paused while the fixture delay calibration data are updated. However, it may be expected that the above described strategy will bring along a reduction with respect to test time.
  • FIG. 12 shows a flow chart of an inventive method for providing a timing information for adjusting a timing of a chip tester.
  • the chip tester operates in a configuration, in which at least a first terminal of a first dut and a first terminal of a second dut are connected to a first channel of the chip tester via a shared line.
  • a second terminal of the first dut is connected to a second channel of the chip tester via an unshared line and that a second terminal of the second dut is connected to a third channel of the chip tester via an unshared line.
  • the method 1200 comprises a second step 1210 of obtaining a propagation delay difference information describing a propagation time difference between, on the one hand, a propagation delay from a first channel port of the chip tester to the first terminal of the first dut and, on the other hand, a propagation delay from the first channel port of the chip tester to the first terminal of the second dut.
  • the method 1200 comprises a second step of providing a timing information to adjust a timing shift between timings of a second channel of the chip tester and a third channel of the chip tester on the basis of the propagation time difference information.
  • the method 1200 of FIG. 12 may be supplemented by any of the functionalities described with respect to the other means and methods herein.
  • the present invention comprises a computer program for performing any of the methods described herein.
  • the inventive methods can be implemented in hardware or in software.
  • the implementation can be performed using a digital storage medium, in for example a hard disk, floppy disk, a DVD a CD, a ROM, a PROM, an EPROM, an EEPROM or a FLASH memory having electronically readable control signals stored thereon, which cooperate with a programmable computer system such that the inventive method is performed.
  • the present invention is, therefore, a computer program product with a program code stored on a machine readable carrier, the program code being operative for performing the inventive method when the computer program product runs on a computer.
  • the inventive method is, therefore, a computer program having a program code for performing the inventive method when the computer program runs on a computer.
  • fixture delay calibration files as described in the procedure fixture_delay_calibration( ) is done, according to an embodiment of the present invention, by the interface manufacturer.
  • the algorithm can be described by the following routines, wherein the expression “//” designates a comment, wherein a loop to be repeated for a plurality of values is described by “loop for . . . end loop”. Moreover, loops are further illustrated by indenting instructions within a loop.
  • fd[1:N] fixture delay calibration files from DUT[1:N,1:K]) ⁇ //Analyze
  • the description provides an overview of a solution proposal for a fixture delay calibration when using driving sharing interfaces.
  • the problem underlying the present invention can be summarized as follows: Due to a sharing of single tester driver channels for multiple device inputs, multiple different propagation delays in the interface may need to be compensated for each shared driver. The compensation should take into account a signal path from a pogo interface to individual duts connected to a shared bus. Since fixture delay calibration delay can only compensate a single path to one dut board, the above described new solution has been developed to also compensate a signal path to other duts connected to one shared bus. Embodiments of the above described invention allow for an efficient calibration and also bring along the possibility to operate test setups with driver sharing at very high speed without compromising reliability of the test results.

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US12/674,644 2007-08-22 2007-08-22 Chip tester, method for providing timing information, test fixture set, apparatus for post-processing propagation delay information, method for post-processing delay information, chip test set up and method for testing devices under test Active 2028-05-27 US8326565B2 (en)

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CN116068380B (zh) * 2023-03-01 2023-07-07 上海聚跃检测技术有限公司 一种芯片封装测试方法及装置
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CN101784906A (zh) 2010-07-21
EP2142936B1 (de) 2011-04-13
KR101225235B1 (ko) 2013-01-23
ATE505734T1 (de) 2011-04-15
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US20110131000A1 (en) 2011-06-02
EP2142936A1 (de) 2010-01-13

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