DE60214894D1 - Mehrchipmodulhalbleiterbauelemente - Google Patents

Mehrchipmodulhalbleiterbauelemente

Info

Publication number
DE60214894D1
DE60214894D1 DE60214894T DE60214894T DE60214894D1 DE 60214894 D1 DE60214894 D1 DE 60214894D1 DE 60214894 T DE60214894 T DE 60214894T DE 60214894 T DE60214894 T DE 60214894T DE 60214894 D1 DE60214894 D1 DE 60214894D1
Authority
DE
Germany
Prior art keywords
connections
die
flip chip
bump electrodes
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60214894T
Other languages
English (en)
Other versions
DE60214894T2 (de
Inventor
J Wheeler
Philip Rutter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Application granted granted Critical
Publication of DE60214894D1 publication Critical patent/DE60214894D1/de
Publication of DE60214894T2 publication Critical patent/DE60214894T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/40247Connecting the strap to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73205Bump and strap connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dc-Dc Converters (AREA)
DE60214894T 2001-11-27 2002-11-20 Mehrchipmodulhalbleiterbauelemente Expired - Lifetime DE60214894T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0128351 2001-11-27
GBGB0128351.4A GB0128351D0 (en) 2001-11-27 2001-11-27 Multi-chip module semiconductor devices
PCT/IB2002/004908 WO2003046989A2 (en) 2001-11-27 2002-11-20 Multi-chip module semiconductor devices

Publications (2)

Publication Number Publication Date
DE60214894D1 true DE60214894D1 (de) 2006-11-02
DE60214894T2 DE60214894T2 (de) 2007-04-26

Family

ID=9926506

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60214894T Expired - Lifetime DE60214894T2 (de) 2001-11-27 2002-11-20 Mehrchipmodulhalbleiterbauelemente

Country Status (10)

Country Link
US (1) US6919643B2 (de)
EP (1) EP1468449B1 (de)
JP (1) JP2005510878A (de)
CN (1) CN100442504C (de)
AT (1) ATE340412T1 (de)
AU (1) AU2002365494A1 (de)
DE (1) DE60214894T2 (de)
GB (1) GB0128351D0 (de)
TW (1) TWI281731B (de)
WO (1) WO2003046989A2 (de)

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JP4142922B2 (ja) * 2002-09-12 2008-09-03 株式会社ルネサステクノロジ ストロボ制御回路、igbtデバイス、半導体装置および電子機器
JP2004247373A (ja) * 2003-02-12 2004-09-02 Semiconductor Energy Lab Co Ltd 半導体装置
US7929921B2 (en) * 2003-06-10 2011-04-19 Motorola Mobility, Inc. Diversity control in wireless communications devices and methods
JP4658481B2 (ja) * 2004-01-16 2011-03-23 ルネサスエレクトロニクス株式会社 半導体装置
JP4489485B2 (ja) 2004-03-31 2010-06-23 株式会社ルネサステクノロジ 半導体装置
WO2005122249A2 (en) * 2004-06-03 2005-12-22 International Rectifier Corporation Semiconductor device module with flip chip devices on a common lead frame
US7230333B2 (en) * 2005-04-21 2007-06-12 International Rectifier Corporation Semiconductor package
WO2007111480A1 (en) 2006-03-28 2007-10-04 Samsung Electronics Co., Ltd. Method and apparatus for discontinuous reception of connected terminal in a mobile communication system
US7569920B2 (en) * 2006-05-10 2009-08-04 Infineon Technologies Ag Electronic component having at least one vertical semiconductor power transistor
US7271470B1 (en) 2006-05-31 2007-09-18 Infineon Technologies Ag Electronic component having at least two semiconductor power devices
US7683477B2 (en) * 2007-06-26 2010-03-23 Infineon Technologies Ag Semiconductor device including semiconductor chips having contact elements
US8064224B2 (en) * 2008-03-31 2011-11-22 Intel Corporation Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same
US8148815B2 (en) * 2008-10-13 2012-04-03 Intersil Americas, Inc. Stacked field effect transistor configurations
US8168490B2 (en) * 2008-12-23 2012-05-01 Intersil Americas, Inc. Co-packaging approach for power converters based on planar devices, structure and method
EP2202794A3 (de) 2008-12-23 2012-07-04 Intersil Americas Inc. Ausgangsleistungsstufe auf einem Chip mit Grabengate-Low Side- und LDMOS-High Side-MOSFETs, Struktur und Verfahren
JP5381444B2 (ja) * 2009-07-17 2014-01-08 トヨタ自動車株式会社 パワーモジュール
JP5123966B2 (ja) * 2010-03-04 2013-01-23 ルネサスエレクトロニクス株式会社 半導体装置
KR20120123254A (ko) * 2011-04-29 2012-11-08 후아웨이 테크놀러지 컴퍼니 리미티드 전력 공급 모듈 및 이의 패키징 및 집적 방법
EP2707956A1 (de) * 2011-05-10 2014-03-19 ABB Research Ltd. Leistungsmodul und verfahren zum betrieb eines leistungsmoduls
US8614503B2 (en) * 2011-05-19 2013-12-24 International Rectifier Corporation Common drain exposed conductive clip for high power semiconductor packages
CN102832189B (zh) * 2012-09-11 2014-07-16 矽力杰半导体技术(杭州)有限公司 一种多芯片封装结构及其封装方法
JP5493021B2 (ja) * 2013-03-08 2014-05-14 ルネサスエレクトロニクス株式会社 半導体装置
CN103762214B (zh) * 2014-01-24 2016-08-17 矽力杰半导体技术(杭州)有限公司 应用于开关型调节器的集成电路组件
DE102015112502B4 (de) 2015-07-30 2021-11-04 Infineon Technologies Ag Halbleiterbauelemente
WO2017091152A1 (en) * 2015-11-23 2017-06-01 Agency For Science, Technology And Research Wafer level integration of high power switching devices on cmos driver integrated circuit
DE102022111517A1 (de) 2022-05-09 2023-11-09 Infineon Technologies Ag Ein halbleiterbauelement mit einem eingebetteten elektrischen leiter, der zwischen pins eines halbleiterbauelements und einem weiteren bauelement angeschlossen ist
TWI800381B (zh) * 2022-05-19 2023-04-21 璦司柏電子股份有限公司 內建閘極驅動晶片的覆晶封裝功率電晶體模組
CN116190370B (zh) * 2023-04-04 2023-08-22 南京理工大学 一种级联型GaN功率器件封装结构

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JP3123343B2 (ja) 1994-05-11 2001-01-09 富士電機株式会社 安定化電源装置とその製造方法
US5532512A (en) 1994-10-03 1996-07-02 General Electric Company Direct stacked and flip chip power semiconductor device structures
US5608262A (en) * 1995-02-24 1997-03-04 Lucent Technologies Inc. Packaging multi-chip modules without wire-bond interconnection
TW373308B (en) * 1995-02-24 1999-11-01 Agere Systems Inc Thin packaging of multi-chip modules with enhanced thermal/power management
US5869894A (en) * 1997-07-18 1999-02-09 Lucent Technologies Inc. RF IC package
SE520119C2 (sv) 1998-10-13 2003-05-27 Ericsson Telefon Ab L M Förfarande och anordning för hopkoppling av radiofrekvens-SiC-fälteffekttransistorer för högeffekttillämpningar
JP2000294692A (ja) 1999-04-06 2000-10-20 Hitachi Ltd 樹脂封止型電子装置及びその製造方法並びにそれを使用した内燃機関用点火コイル装置
TWI250406B (en) * 2000-03-22 2006-03-01 Int Rectifier Corp Gate driver multi-chip module
KR100559664B1 (ko) * 2000-03-25 2006-03-10 앰코 테크놀로지 코리아 주식회사 반도체패키지
US6600220B2 (en) * 2001-05-14 2003-07-29 Hewlett-Packard Company Power distribution in multi-chip modules

Also Published As

Publication number Publication date
ATE340412T1 (de) 2006-10-15
EP1468449B1 (de) 2006-09-20
TW200409307A (en) 2004-06-01
CN100442504C (zh) 2008-12-10
US20030098468A1 (en) 2003-05-29
DE60214894T2 (de) 2007-04-26
WO2003046989A3 (en) 2003-10-09
JP2005510878A (ja) 2005-04-21
GB0128351D0 (en) 2002-01-16
AU2002365494A1 (en) 2003-06-10
US6919643B2 (en) 2005-07-19
EP1468449A2 (de) 2004-10-20
CN1596473A (zh) 2005-03-16
TWI281731B (en) 2007-05-21
WO2003046989A2 (en) 2003-06-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL