DE60207282D1 - Verkapselung des anschlusslots zur aufrechterhaltung der genauigkeit der anschlussposition - Google Patents
Verkapselung des anschlusslots zur aufrechterhaltung der genauigkeit der anschlusspositionInfo
- Publication number
- DE60207282D1 DE60207282D1 DE60207282T DE60207282T DE60207282D1 DE 60207282 D1 DE60207282 D1 DE 60207282D1 DE 60207282 T DE60207282 T DE 60207282T DE 60207282 T DE60207282 T DE 60207282T DE 60207282 D1 DE60207282 D1 DE 60207282D1
- Authority
- DE
- Germany
- Prior art keywords
- connection
- capture
- accuracy
- maintain
- lot
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910000679 solder Inorganic materials 0.000 abstract 2
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 239000000155 melt Substances 0.000 abstract 1
- 238000004377 microelectronic Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/1031—Surface mounted metallic connector elements
- H05K2201/10318—Surface mounted metallic pins
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Wire Bonding (AREA)
- Multi-Conductor Connections (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Mechanical Coupling Of Light Guides (AREA)
- Flanged Joints, Insulating Joints, And Other Joints (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US965555 | 2001-09-27 | ||
US09/965,555 US6974765B2 (en) | 2001-09-27 | 2001-09-27 | Encapsulation of pin solder for maintaining accuracy in pin position |
PCT/US2002/030625 WO2003028100A2 (en) | 2001-09-27 | 2002-09-26 | Encapsulation of pin solder for maintaining accuracy in pin position |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60207282D1 true DE60207282D1 (de) | 2005-12-15 |
DE60207282T2 DE60207282T2 (de) | 2006-05-24 |
Family
ID=25510133
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60207282T Expired - Lifetime DE60207282T2 (de) | 2001-09-27 | 2002-09-26 | Verkapselung des anschlusslots zur aufrechterhaltung der genauigkeit der anschlussposition |
Country Status (6)
Country | Link |
---|---|
US (2) | US6974765B2 (de) |
EP (1) | EP1430532B1 (de) |
CN (1) | CN100350603C (de) |
AT (1) | ATE309616T1 (de) |
DE (1) | DE60207282T2 (de) |
WO (1) | WO2003028100A2 (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6303423B1 (en) * | 1998-12-21 | 2001-10-16 | Megic Corporation | Method for forming high performance system-on-chip using post passivation process |
US8178435B2 (en) | 1998-12-21 | 2012-05-15 | Megica Corporation | High performance system-on-chip inductor using post passivation process |
US8421158B2 (en) | 1998-12-21 | 2013-04-16 | Megica Corporation | Chip structure with a passive device and method for forming the same |
US6974765B2 (en) * | 2001-09-27 | 2005-12-13 | Intel Corporation | Encapsulation of pin solder for maintaining accuracy in pin position |
US6911726B2 (en) * | 2002-06-07 | 2005-06-28 | Intel Corporation | Microelectronic packaging and methods for thermally protecting package interconnects and components |
TWI236763B (en) * | 2003-05-27 | 2005-07-21 | Megic Corp | High performance system-on-chip inductor using post passivation process |
US7417305B2 (en) * | 2004-08-26 | 2008-08-26 | Micron Technology, Inc. | Electronic devices at the wafer level having front side and edge protection material and systems including the devices |
US8384189B2 (en) * | 2005-03-29 | 2013-02-26 | Megica Corporation | High performance system-on-chip using post passivation process |
US20080283999A1 (en) * | 2007-05-18 | 2008-11-20 | Eric Tosaya | Chip Package with Pin Stabilization Layer |
JP4993754B2 (ja) * | 2008-02-22 | 2012-08-08 | 新光電気工業株式会社 | Pga型配線基板及びその製造方法 |
JP4961398B2 (ja) * | 2008-06-30 | 2012-06-27 | 株式会社日立製作所 | 半導体装置 |
JP5281346B2 (ja) * | 2008-09-18 | 2013-09-04 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
CN102291974B (zh) * | 2010-06-18 | 2014-04-02 | 亚旭电脑股份有限公司 | 切边定位型焊接垫及防止引脚偏移的方法 |
JP2012164965A (ja) * | 2011-01-21 | 2012-08-30 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
EP3859776A1 (de) * | 2020-01-31 | 2021-08-04 | Infineon Technologies AG | Leistungshalbleiterbauelement und verfahren zur herstellung eines leistungshalbleiterbauelements |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4233620A (en) | 1979-02-27 | 1980-11-11 | International Business Machines Corporation | Sealing of integrated circuit modules |
JP2573225B2 (ja) * | 1987-02-10 | 1997-01-22 | 株式会社東芝 | 電子部品の製造方法 |
US5088914A (en) * | 1990-05-11 | 1992-02-18 | Romano Brambilla | Double flighted extrusion screw |
US5196251A (en) | 1991-04-30 | 1993-03-23 | International Business Machines Corporation | Ceramic substrate having a protective coating thereon and a method for protecting a ceramic substrate |
US5469333A (en) * | 1993-05-05 | 1995-11-21 | International Business Machines Corporation | Electronic package assembly with protective encapsulant material on opposing sides not having conductive leads |
DE69220333D1 (de) * | 1991-12-11 | 1997-07-17 | Ibm | Elektronische Baugruppe mit schützendem Verkapselungsmaterial |
US5288944A (en) * | 1992-02-18 | 1994-02-22 | International Business Machines, Inc. | Pinned ceramic chip carrier |
US5243133A (en) * | 1992-02-18 | 1993-09-07 | International Business Machines, Inc. | Ceramic chip carrier with lead frame or edge clip |
US5249101A (en) * | 1992-07-06 | 1993-09-28 | International Business Machines Corporation | Chip carrier with protective coating for circuitized surface |
US5303862A (en) | 1992-12-31 | 1994-04-19 | International Business Machines Corporation | Single step electrical/mechanical connection process for connecting I/O pins and creating multilayer structures |
KR100339767B1 (ko) * | 1993-12-09 | 2002-11-30 | 메소드 일렉트로닉스 인코포레이티드 | 전기신호전달용전기커넥터및그제조방법 |
US5435482A (en) * | 1994-02-04 | 1995-07-25 | Lsi Logic Corporation | Integrated circuit having a coplanar solder ball contact array |
JPH0823160A (ja) * | 1994-05-06 | 1996-01-23 | Seiko Epson Corp | プリント配線板と電子部品の接続方法 |
JPH0945844A (ja) | 1995-07-31 | 1997-02-14 | Sumitomo Kinzoku Electro Device:Kk | 低温焼成セラミック基板の外部i/oピン接合構造及びその製造方法 |
JPH09102560A (ja) | 1995-10-05 | 1997-04-15 | Sumitomo Kinzoku Electro Device:Kk | 低温焼成セラミック基板の外部リードピン接合構造 |
JP3037885B2 (ja) | 1995-10-31 | 2000-05-08 | 日本特殊陶業株式会社 | Pga型電子部品用基板 |
JPH09129769A (ja) | 1995-11-06 | 1997-05-16 | Sumitomo Kinzoku Erekutorodebaisu:Kk | セラミックパッケージ |
US5708056A (en) * | 1995-12-04 | 1998-01-13 | Delco Electronics Corporation | Hot melt epoxy encapsulation material |
US5891754A (en) * | 1997-02-11 | 1999-04-06 | Delco Electronics Corp. | Method of inspecting integrated circuit solder joints with x-ray detectable encapsulant |
JP2001510944A (ja) * | 1997-07-21 | 2001-08-07 | アギラ テクノロジーズ インコーポレイテッド | 半導体フリップチップ・パッケージおよびその製造方法 |
US6353182B1 (en) * | 1997-08-18 | 2002-03-05 | International Business Machines Corporation | Proper choice of the encapsulant volumetric CTE for different PGBA substrates |
JP3381601B2 (ja) * | 1998-01-26 | 2003-03-04 | 松下電器産業株式会社 | バンプ付電子部品の実装方法 |
US6229207B1 (en) * | 2000-01-13 | 2001-05-08 | Advanced Micro Devices, Inc. | Organic pin grid array flip chip carrier package |
US6578755B1 (en) * | 2000-09-22 | 2003-06-17 | Flip Chip Technologies, L.L.C. | Polymer collar for solder bumps |
TW527676B (en) * | 2001-01-19 | 2003-04-11 | Matsushita Electric Ind Co Ltd | Photo-semiconductor module and method for manufacturing |
US7242099B2 (en) * | 2001-03-05 | 2007-07-10 | Megica Corporation | Chip package with multiple chips connected by bumps |
JP2002359328A (ja) * | 2001-03-29 | 2002-12-13 | Hitachi Ltd | 半導体装置 |
US6974765B2 (en) * | 2001-09-27 | 2005-12-13 | Intel Corporation | Encapsulation of pin solder for maintaining accuracy in pin position |
US6610559B2 (en) * | 2001-11-16 | 2003-08-26 | Indium Corporation Of America | Integrated void-free process for assembling a solder bumped chip |
JP2004281634A (ja) * | 2003-03-14 | 2004-10-07 | Renesas Technology Corp | 積層実装型半導体装置の製造方法 |
-
2001
- 2001-09-27 US US09/965,555 patent/US6974765B2/en not_active Expired - Fee Related
-
2002
- 2002-09-26 EP EP02799643A patent/EP1430532B1/de not_active Expired - Lifetime
- 2002-09-26 WO PCT/US2002/030625 patent/WO2003028100A2/en not_active Application Discontinuation
- 2002-09-26 DE DE60207282T patent/DE60207282T2/de not_active Expired - Lifetime
- 2002-09-26 AT AT02799643T patent/ATE309616T1/de not_active IP Right Cessation
- 2002-09-26 CN CNB028190548A patent/CN100350603C/zh not_active Expired - Fee Related
-
2003
- 2003-07-23 US US10/626,117 patent/US7211888B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1572023A (zh) | 2005-01-26 |
WO2003028100A2 (en) | 2003-04-03 |
DE60207282T2 (de) | 2006-05-24 |
WO2003028100A3 (en) | 2003-11-20 |
EP1430532A2 (de) | 2004-06-23 |
ATE309616T1 (de) | 2005-11-15 |
CN100350603C (zh) | 2007-11-21 |
US20050275094A1 (en) | 2005-12-15 |
US7211888B2 (en) | 2007-05-01 |
US20030057572A1 (en) | 2003-03-27 |
EP1430532B1 (de) | 2005-11-09 |
US6974765B2 (en) | 2005-12-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |