DE602007001311D1 - Halbleiterspeicher mit Daten-Adressen-Multiplex auf dem Adressbus - Google Patents

Halbleiterspeicher mit Daten-Adressen-Multiplex auf dem Adressbus

Info

Publication number
DE602007001311D1
DE602007001311D1 DE602007001311T DE602007001311T DE602007001311D1 DE 602007001311 D1 DE602007001311 D1 DE 602007001311D1 DE 602007001311 T DE602007001311 T DE 602007001311T DE 602007001311 T DE602007001311 T DE 602007001311T DE 602007001311 D1 DE602007001311 D1 DE 602007001311D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
address
multiplexing
data
address bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007001311T
Other languages
English (en)
Inventor
Tatsuya Kanda
Kotoku Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Publication of DE602007001311D1 publication Critical patent/DE602007001311D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
DE602007001311T 2006-07-12 2007-02-28 Halbleiterspeicher mit Daten-Adressen-Multiplex auf dem Adressbus Active DE602007001311D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006191685A JP5087870B2 (ja) 2006-07-12 2006-07-12 半導体メモリ、コントローラおよび半導体メモリの動作方法

Publications (1)

Publication Number Publication Date
DE602007001311D1 true DE602007001311D1 (de) 2009-07-30

Family

ID=38565568

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007001311T Active DE602007001311D1 (de) 2006-07-12 2007-02-28 Halbleiterspeicher mit Daten-Adressen-Multiplex auf dem Adressbus

Country Status (6)

Country Link
US (1) US7684258B2 (de)
EP (1) EP1879196B1 (de)
JP (1) JP5087870B2 (de)
KR (1) KR100909407B1 (de)
CN (1) CN101105972B (de)
DE (1) DE602007001311D1 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7788438B2 (en) * 2006-10-13 2010-08-31 Macronix International Co., Ltd. Multi-input/output serial peripheral interface and method for data transmission
JP2008198280A (ja) * 2007-02-13 2008-08-28 Elpida Memory Inc 半導体記憶装置及びその動作方法
US8581920B2 (en) * 2007-09-27 2013-11-12 Rambus Inc. Utilizing masked data bits during accesses to a memory
JP2009187615A (ja) * 2008-02-05 2009-08-20 Elpida Memory Inc 半導体記憶装置
JP2009211735A (ja) * 2008-02-29 2009-09-17 Toshiba Corp 不揮発性記憶装置
US8045416B2 (en) * 2008-03-05 2011-10-25 Micron Technology, Inc. Method and memory device providing reduced quantity of interconnections
US7983108B2 (en) * 2008-08-04 2011-07-19 Micron Technology, Inc. Row mask addressing
US8407427B2 (en) * 2008-10-29 2013-03-26 Silicon Image, Inc. Method and system for improving serial port memory communication latency and reliability
KR100968417B1 (ko) 2008-11-06 2010-07-07 주식회사 하이닉스반도체 반도체 메모리 장치
KR20110012804A (ko) * 2009-07-31 2011-02-09 삼성전자주식회사 데이터 마스크 시스템 및 데이터 마스크 방법
JP2011180848A (ja) 2010-03-01 2011-09-15 Elpida Memory Inc 半導体装置及びこれを備える情報処理システム、並びに、半導体装置を制御するコントローラ
KR101223537B1 (ko) * 2010-10-29 2013-01-21 에스케이하이닉스 주식회사 반도체 메모리 장치
JP2014082245A (ja) * 2012-10-15 2014-05-08 J Devices:Kk 半導体記憶装置及びその製造方法
KR20150019317A (ko) * 2013-08-13 2015-02-25 에스케이하이닉스 주식회사 메모리 및 이를 포함 하는 메모리 시스템
JP5902137B2 (ja) * 2013-09-24 2016-04-13 株式会社東芝 ストレージシステム
KR102122892B1 (ko) * 2013-09-25 2020-06-15 에스케이하이닉스 주식회사 메모리 및 이를 포함하는 메모리 시스템
US9396786B2 (en) 2013-09-25 2016-07-19 SK Hynix Inc. Memory and memory system including the same
US9613685B1 (en) * 2015-11-13 2017-04-04 Texas Instruments Incorporated Burst mode read controllable SRAM
JP6370953B1 (ja) 2017-03-23 2018-08-08 ファナック株式会社 マルチランクｓｄｒａｍ制御方法及びｓｄｒａｍコントローラ
KR102300123B1 (ko) * 2017-06-01 2021-09-09 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
KR102558827B1 (ko) * 2018-01-02 2023-07-24 삼성전자주식회사 반도체 메모리 장치, 및 이 장치를 구비하는 메모리 시스템 및 전자 장치
KR102634962B1 (ko) * 2018-09-06 2024-02-08 에스케이하이닉스 주식회사 반도체장치
US10910037B2 (en) * 2018-10-04 2021-02-02 Micron Technology, Inc. Apparatuses and methods for input receiver circuits and receiver masks for same
KR20200091201A (ko) * 2019-01-22 2020-07-30 에스케이하이닉스 주식회사 메모리 시스템

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6150281A (ja) 1985-07-26 1986-03-12 Hitachi Ltd メモリ
JPH02177190A (ja) 1988-12-28 1990-07-10 Nec Corp メモリ装置
JPH02246087A (ja) * 1989-03-20 1990-10-01 Hitachi Ltd 半導体記憶装置ならびにその冗長方式及びレイアウト方式
JPH0528760A (ja) * 1991-07-24 1993-02-05 Nec Corp 半導体メモリ
US6088760A (en) * 1997-03-07 2000-07-11 Mitsubishi Semiconductor America, Inc. Addressing system in a multi-port RAM having main and cache memories
JP3259696B2 (ja) 1998-10-27 2002-02-25 日本電気株式会社 同期型半導体記憶装置
JP2001035153A (ja) * 1999-07-23 2001-02-09 Fujitsu Ltd 半導体記憶装置
KR20010037711A (ko) 1999-10-19 2001-05-15 박종섭 반도체 소자의 어드레스 입출력 제어방법
JP3779524B2 (ja) 2000-04-20 2006-05-31 株式会社東芝 マルチチップ半導体装置及びメモリカード
JP4768163B2 (ja) * 2001-08-03 2011-09-07 富士通セミコンダクター株式会社 半導体メモリ
KR100498466B1 (ko) * 2002-11-30 2005-07-01 삼성전자주식회사 개선된 데이터 기입 제어 회로를 가지는 4비트 프리페치방식 ｆｃｒａｍ 및 이에 대한 데이터 마스킹 방법
JP4614650B2 (ja) * 2003-11-13 2011-01-19 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP2005182530A (ja) * 2003-12-19 2005-07-07 Matsushita Electric Ind Co Ltd メモリインターフェース装置、およびメモリインターフェース制御方法
JP4827399B2 (ja) * 2004-05-26 2011-11-30 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7145816B2 (en) * 2004-08-16 2006-12-05 Micron Technology, Inc. Using redundant memory for extra features
JP2009187615A (ja) * 2008-02-05 2009-08-20 Elpida Memory Inc 半導体記憶装置

Also Published As

Publication number Publication date
JP2008021364A (ja) 2008-01-31
CN101105972A (zh) 2008-01-16
JP5087870B2 (ja) 2012-12-05
EP1879196A1 (de) 2008-01-16
KR100909407B1 (ko) 2009-07-24
US20080025127A1 (en) 2008-01-31
CN101105972B (zh) 2012-02-29
EP1879196B1 (de) 2009-06-17
US7684258B2 (en) 2010-03-23
KR20080006442A (ko) 2008-01-16

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Legal Events

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8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP