DE602005023584D1 - Inversionsbitleitung, nicht flüchtiger Ladungsabfangspeicher und Verfahren zu dessen Betrieb - Google Patents

Inversionsbitleitung, nicht flüchtiger Ladungsabfangspeicher und Verfahren zu dessen Betrieb

Info

Publication number
DE602005023584D1
DE602005023584D1 DE602005023584T DE602005023584T DE602005023584D1 DE 602005023584 D1 DE602005023584 D1 DE 602005023584D1 DE 602005023584 T DE602005023584 T DE 602005023584T DE 602005023584 T DE602005023584 T DE 602005023584T DE 602005023584 D1 DE602005023584 D1 DE 602005023584D1
Authority
DE
Germany
Prior art keywords
bit line
charge trap
inversion bit
nonvolatile charge
nonvolatile
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005023584T
Other languages
English (en)
Inventor
Hsiang-Lan Lung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Macronix International Co Ltd
Original Assignee
Macronix International Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix International Co Ltd filed Critical Macronix International Co Ltd
Publication of DE602005023584D1 publication Critical patent/DE602005023584D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
DE602005023584T 2005-04-29 2005-05-19 Inversionsbitleitung, nicht flüchtiger Ladungsabfangspeicher und Verfahren zu dessen Betrieb Active DE602005023584D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/118,839 US7158420B2 (en) 2005-04-29 2005-04-29 Inversion bit line, charge trapping non-volatile memory and method of operating same

Publications (1)

Publication Number Publication Date
DE602005023584D1 true DE602005023584D1 (de) 2010-10-28

Family

ID=34936696

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005023584T Active DE602005023584D1 (de) 2005-04-29 2005-05-19 Inversionsbitleitung, nicht flüchtiger Ladungsabfangspeicher und Verfahren zu dessen Betrieb

Country Status (5)

Country Link
US (1) US7158420B2 (de)
EP (1) EP1717815B1 (de)
JP (1) JP5259918B2 (de)
CN (1) CN1855510B (de)
DE (1) DE602005023584D1 (de)

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Also Published As

Publication number Publication date
US7158420B2 (en) 2007-01-02
EP1717815A1 (de) 2006-11-02
EP1717815B1 (de) 2010-09-15
CN1855510A (zh) 2006-11-01
US20060245246A1 (en) 2006-11-02
CN1855510B (zh) 2010-09-08
JP2006310720A (ja) 2006-11-09
JP5259918B2 (ja) 2013-08-07

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