DE602005019749D1 - Speicherstapelungssystem und -verfahren - Google Patents

Speicherstapelungssystem und -verfahren

Info

Publication number
DE602005019749D1
DE602005019749D1 DE602005019749T DE602005019749T DE602005019749D1 DE 602005019749 D1 DE602005019749 D1 DE 602005019749D1 DE 602005019749 T DE602005019749 T DE 602005019749T DE 602005019749 T DE602005019749 T DE 602005019749T DE 602005019749 D1 DE602005019749 D1 DE 602005019749D1
Authority
DE
Germany
Prior art keywords
memory module
high density
modified
memory devices
decoding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005019749T
Other languages
English (en)
Inventor
Thomas H Kinsley
Kevin M Kilbuck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE602005019749D1 publication Critical patent/DE602005019749D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Semiconductor Memories (AREA)
DE602005019749T 2004-09-01 2005-08-30 Speicherstapelungssystem und -verfahren Active DE602005019749D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/932,834 US7046538B2 (en) 2004-09-01 2004-09-01 Memory stacking system and method
PCT/US2005/030864 WO2006028823A1 (en) 2004-09-01 2005-08-30 Memory stacking system and method

Publications (1)

Publication Number Publication Date
DE602005019749D1 true DE602005019749D1 (de) 2010-04-15

Family

ID=35645096

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005019749T Active DE602005019749D1 (de) 2004-09-01 2005-08-30 Speicherstapelungssystem und -verfahren

Country Status (8)

Country Link
US (2) US7046538B2 (de)
EP (1) EP1784831B1 (de)
JP (1) JP2008511927A (de)
KR (1) KR20070056110A (de)
AT (1) ATE459960T1 (de)
DE (1) DE602005019749D1 (de)
TW (1) TWI282557B (de)
WO (1) WO2006028823A1 (de)

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Also Published As

Publication number Publication date
EP1784831A1 (de) 2007-05-16
JP2008511927A (ja) 2008-04-17
US20060044860A1 (en) 2006-03-02
ATE459960T1 (de) 2010-03-15
US7046538B2 (en) 2006-05-16
TW200620302A (en) 2006-06-16
US7269042B2 (en) 2007-09-11
WO2006028823A1 (en) 2006-03-16
EP1784831B1 (de) 2010-03-03
TWI282557B (en) 2007-06-11
KR20070056110A (ko) 2007-05-31
US20060198178A1 (en) 2006-09-07

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