ATE339006T1 - Pufferanordnung für speicher - Google Patents
Pufferanordnung für speicherInfo
- Publication number
- ATE339006T1 ATE339006T1 AT03731546T AT03731546T ATE339006T1 AT E339006 T1 ATE339006 T1 AT E339006T1 AT 03731546 T AT03731546 T AT 03731546T AT 03731546 T AT03731546 T AT 03731546T AT E339006 T1 ATE339006 T1 AT E339006T1
- Authority
- AT
- Austria
- Prior art keywords
- memory
- devices
- storage
- buffer
- buffer arrangement
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
Landscapes
- Memory System (AREA)
- Dram (AREA)
- Non-Volatile Memory (AREA)
- Oscillators With Electromechanical Resonators (AREA)
- Vehicle Body Suspensions (AREA)
- Read Only Memory (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Information Transfer Systems (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/186,357 US6639820B1 (en) | 2002-06-27 | 2002-06-27 | Memory buffer arrangement |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE339006T1 true ATE339006T1 (de) | 2006-09-15 |
Family
ID=29250181
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT03731546T ATE339006T1 (de) | 2002-06-27 | 2003-05-22 | Pufferanordnung für speicher |
Country Status (9)
Country | Link |
---|---|
US (1) | US6639820B1 (de) |
EP (1) | EP1516339B1 (de) |
KR (1) | KR100647162B1 (de) |
CN (1) | CN1679108B (de) |
AT (1) | ATE339006T1 (de) |
AU (1) | AU2003240534A1 (de) |
DE (1) | DE60308183T2 (de) |
TW (1) | TWI290322B (de) |
WO (1) | WO2004003916A1 (de) |
Families Citing this family (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7363422B2 (en) * | 2000-01-05 | 2008-04-22 | Rambus Inc. | Configurable width buffered module |
US20050010737A1 (en) * | 2000-01-05 | 2005-01-13 | Fred Ware | Configurable width buffered module having splitter elements |
US7356639B2 (en) * | 2000-01-05 | 2008-04-08 | Rambus Inc. | Configurable width buffered module having a bypass circuit |
US7120765B2 (en) * | 2002-10-30 | 2006-10-10 | Intel Corporation | Memory transaction ordering |
US8250295B2 (en) | 2004-01-05 | 2012-08-21 | Smart Modular Technologies, Inc. | Multi-rank memory module that emulates a memory module having a different number of ranks |
DE102004004026A1 (de) * | 2004-01-27 | 2005-08-18 | Infineon Technologies Ag | Schaltungsanordnung zur Datenspeicherung |
US20060129712A1 (en) * | 2004-12-10 | 2006-06-15 | Siva Raghuram | Buffer chip for a multi-rank dual inline memory module (DIMM) |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US20080028136A1 (en) | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US7392338B2 (en) | 2006-07-31 | 2008-06-24 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US7386656B2 (en) | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US20060294295A1 (en) * | 2005-06-24 | 2006-12-28 | Yukio Fukuzo | DRAM chip device well-communicated with flash memory chip and multi-chip package comprising such a device |
US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US7590796B2 (en) * | 2006-07-31 | 2009-09-15 | Metaram, Inc. | System and method for power management in memory systems |
US7472220B2 (en) | 2006-07-31 | 2008-12-30 | Metaram, Inc. | Interface circuit system and method for performing power management operations utilizing power management signals |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
WO2007028109A2 (en) | 2005-09-02 | 2007-03-08 | Metaram, Inc. | Methods and apparatus of stacking drams |
US7966446B2 (en) * | 2005-09-12 | 2011-06-21 | Samsung Electronics Co., Ltd. | Memory system and method having point-to-point link |
US7930492B2 (en) * | 2005-09-12 | 2011-04-19 | Samsung Electronics Co., Ltd. | Memory system having low power consumption |
KR100871835B1 (ko) * | 2007-01-05 | 2008-12-03 | 삼성전자주식회사 | 메모리 시스템 및 메모리 시스템의 신호전송 방법 |
US7464225B2 (en) | 2005-09-26 | 2008-12-09 | Rambus Inc. | Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology |
US11328764B2 (en) | 2005-09-26 | 2022-05-10 | Rambus Inc. | Memory system topologies including a memory die stack |
US7562271B2 (en) | 2005-09-26 | 2009-07-14 | Rambus Inc. | Memory system topologies including a buffer device and an integrated circuit memory device |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US20070290333A1 (en) * | 2006-06-16 | 2007-12-20 | Intel Corporation | Chip stack with a higher power chip on the outside of the stack |
US7724589B2 (en) | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
KR100810613B1 (ko) * | 2006-08-04 | 2008-03-07 | 삼성전자주식회사 | 개별소자들의 개선된 배치 구조를 갖는 메모리 모듈 |
US7761624B2 (en) * | 2006-09-28 | 2010-07-20 | Virident Systems, Inc. | Systems and apparatus for main memory with non-volatile type memory modules, and related technologies |
DE102006051514B4 (de) * | 2006-10-31 | 2010-01-21 | Qimonda Ag | Speichermodul und Verfahren zum Betreiben eines Speichermoduls |
US20080123305A1 (en) * | 2006-11-28 | 2008-05-29 | Smart Modular Technologies, Inc. | Multi-channel memory modules for computing devices |
US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
US8001434B1 (en) | 2008-04-14 | 2011-08-16 | Netlist, Inc. | Memory board with self-testing capability |
WO2010144624A1 (en) | 2009-06-09 | 2010-12-16 | Google Inc. | Programming of dimm termination resistance values |
KR102094393B1 (ko) | 2013-11-18 | 2020-03-27 | 삼성전자주식회사 | 불휘발성 메모리 시스템 및 그것의 동작 방법 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62104149A (ja) * | 1985-10-30 | 1987-05-14 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | 集積回路チツプ・モジユ−ル |
AU628547B2 (en) * | 1989-05-19 | 1992-09-17 | Compaq Computer Corporation | Modular computer memory circuit board |
US5272664A (en) * | 1993-04-21 | 1993-12-21 | Silicon Graphics, Inc. | High memory capacity DRAM SIMM |
US5434745A (en) * | 1994-07-26 | 1995-07-18 | White Microelectronics Div. Of Bowmar Instrument Corp. | Stacked silicon die carrier assembly |
AU1798999A (en) * | 1997-12-05 | 1999-06-28 | Intel Corporation | Memory system including a memory module having a memory module controller |
US6487102B1 (en) * | 2000-09-18 | 2002-11-26 | Intel Corporation | Memory module having buffer for isolating stacked memory devices |
US6317352B1 (en) * | 2000-09-18 | 2001-11-13 | Intel Corporation | Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules |
US6493250B2 (en) | 2000-12-28 | 2002-12-10 | Intel Corporation | Multi-tier point-to-point buffered memory interface |
US6542393B1 (en) * | 2002-04-24 | 2003-04-01 | Ma Laboratories, Inc. | Dual-bank memory module with stacked DRAM chips having a concave-shaped re-route PCB in-between |
-
2002
- 2002-06-27 US US10/186,357 patent/US6639820B1/en not_active Expired - Lifetime
-
2003
- 2003-05-22 KR KR1020047021085A patent/KR100647162B1/ko not_active IP Right Cessation
- 2003-05-22 AU AU2003240534A patent/AU2003240534A1/en not_active Abandoned
- 2003-05-22 WO PCT/US2003/017618 patent/WO2004003916A1/en active IP Right Grant
- 2003-05-22 CN CN038202107A patent/CN1679108B/zh not_active Expired - Fee Related
- 2003-05-22 DE DE60308183T patent/DE60308183T2/de not_active Expired - Lifetime
- 2003-05-22 EP EP03731546A patent/EP1516339B1/de not_active Expired - Lifetime
- 2003-05-22 AT AT03731546T patent/ATE339006T1/de not_active IP Right Cessation
- 2003-06-26 TW TW092117439A patent/TWI290322B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR20050012832A (ko) | 2005-02-02 |
TW200407904A (en) | 2004-05-16 |
DE60308183T2 (de) | 2007-08-23 |
CN1679108B (zh) | 2011-08-17 |
DE60308183D1 (de) | 2006-10-19 |
TWI290322B (en) | 2007-11-21 |
CN1679108A (zh) | 2005-10-05 |
US6639820B1 (en) | 2003-10-28 |
KR100647162B1 (ko) | 2006-11-23 |
EP1516339A1 (de) | 2005-03-23 |
WO2004003916A1 (en) | 2004-01-08 |
EP1516339B1 (de) | 2006-09-06 |
AU2003240534A1 (en) | 2004-01-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |