DE602004001679D1 - Speichersystem mit sequenziell ausgeführten schnellen und langsamen lesezugriffen - Google Patents

Speichersystem mit sequenziell ausgeführten schnellen und langsamen lesezugriffen

Info

Publication number
DE602004001679D1
DE602004001679D1 DE200460001679 DE602004001679T DE602004001679D1 DE 602004001679 D1 DE602004001679 D1 DE 602004001679D1 DE 200460001679 DE200460001679 DE 200460001679 DE 602004001679 T DE602004001679 T DE 602004001679T DE 602004001679 D1 DE602004001679 D1 DE 602004001679D1
Authority
DE
Germany
Prior art keywords
sequencelally
storage system
slow reading
quick
executed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE200460001679
Other languages
English (en)
Other versions
DE602004001679T2 (de
Inventor
Michael Austin
Theodore Blaauw
Nigel Mudge
Krisztian Flautner
Michael Sylvester
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Ltd
University of Michigan
Original Assignee
ARM Ltd
Advanced Risc Machines Ltd
University of Michigan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/392,382 external-priority patent/US7278080B2/en
Application filed by ARM Ltd, Advanced Risc Machines Ltd, University of Michigan filed Critical ARM Ltd
Publication of DE602004001679D1 publication Critical patent/DE602004001679D1/de
Application granted granted Critical
Publication of DE602004001679T2 publication Critical patent/DE602004001679T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/141—Saving, restoring, recovering or retrying at machine instruction level for bus or memory accesses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)
DE200460001679 2003-03-20 2004-03-17 Speichersystem mit sequenziell ausgeführten schnellen und langsamen lesezugriffen Expired - Lifetime DE602004001679T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US392382 2003-03-20
US10/392,382 US7278080B2 (en) 2003-03-20 2003-03-20 Error detection and recovery within processing stages of an integrated circuit
US779809 2004-02-18
US10/779,809 US6944067B2 (en) 2003-03-20 2004-02-18 Memory system having fast and slow data reading mechanisms
PCT/GB2004/001137 WO2004084233A1 (en) 2003-03-20 2004-03-17 Momory system having fast and slow data reading mechanisms

Publications (2)

Publication Number Publication Date
DE602004001679D1 true DE602004001679D1 (de) 2006-09-07
DE602004001679T2 DE602004001679T2 (de) 2007-08-02

Family

ID=33032649

Family Applications (1)

Application Number Title Priority Date Filing Date
DE200460001679 Expired - Lifetime DE602004001679T2 (de) 2003-03-20 2004-03-17 Speichersystem mit sequenziell ausgeführten schnellen und langsamen lesezugriffen

Country Status (7)

Country Link
US (1) US7072229B2 (de)
EP (1) EP1604371B1 (de)
JP (1) JP4279874B2 (de)
KR (1) KR100955285B1 (de)
DE (1) DE602004001679T2 (de)
RU (1) RU2005129281A (de)
WO (1) WO2004084233A1 (de)

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KR100582391B1 (ko) * 2004-04-08 2006-05-22 주식회사 하이닉스반도체 반도체 소자에서의 지연 요소의 지연 검출 장치 및 방법
US7840875B2 (en) * 2006-05-15 2010-11-23 Sandisk Corporation Convolutional coding methods for nonvolatile memory
US20070266296A1 (en) * 2006-05-15 2007-11-15 Conley Kevin M Nonvolatile Memory with Convolutional Coding
TWI397822B (zh) * 2006-11-13 2013-06-01 Via Tech Inc 串列週邊介面控制裝置及串列週邊介面系統以及串列週邊介面裝置之判斷方法
US9280419B2 (en) * 2013-12-16 2016-03-08 International Business Machines Corporation Dynamic adjustment of data protection schemes in flash storage systems based on temperature, power off duration and flash age
US10565048B2 (en) 2017-12-01 2020-02-18 Arista Networks, Inc. Logic buffer for hitless single event upset handling
KR20210058566A (ko) 2019-11-14 2021-05-24 삼성전자주식회사 전자 시스템, 그것의 결함 검출 방법, 시스템 온 칩 및 버스 시스템
KR20210062278A (ko) * 2019-11-21 2021-05-31 주식회사 메타씨앤아이 메모리 장치
US11967360B2 (en) * 2021-09-22 2024-04-23 Arm Limited Dynamically adjustable pipeline for memory access

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US618861A (en) * 1899-02-07 Process of and apparatus for manufacturing sheet-glass
SU809350A1 (ru) * 1979-05-31 1981-02-28 Московский Ордена Трудовогокрасного Знамени Текстильныйинститут Запоминающее устройство
JPS6020398A (ja) * 1983-07-14 1985-02-01 Nec Corp メモリ装置
JPS6224498A (ja) * 1985-07-24 1987-02-02 Nippon Telegr & Teleph Corp <Ntt> メモリ読出し方式
US4994993A (en) 1988-10-26 1991-02-19 Advanced Micro Devices, Inc. System for detecting and correcting errors generated by arithmetic logic units
US4926374A (en) 1988-11-23 1990-05-15 International Business Machines Corporation Residue checking apparatus for detecting errors in add, subtract, multiply, divide and square root operations
JPH03142629A (ja) * 1989-10-30 1991-06-18 Toshiba Corp マイクロコントローラ
US5203003A (en) * 1991-03-28 1993-04-13 Echelon Corporation Computer architecture for conserving power by using shared resources and method for suspending processor execution in pipeline
EP0653708B1 (de) 1993-10-15 2000-08-16 Hitachi, Ltd. Logischer Schaltkreis mit Fehlernachweisfunktion, Verfahren zum Verwalten von Betriebsmitteln und fehlertolerantes System zu seiner Anwendung
US5734585A (en) * 1994-11-07 1998-03-31 Norand Corporation Method and apparatus for sequencing power delivery in mixed supply computer systems
US5615263A (en) * 1995-01-06 1997-03-25 Vlsi Technology, Inc. Dual purpose security architecture with protected internal operating system
JP3494849B2 (ja) * 1997-05-29 2004-02-09 富士通株式会社 半導体記憶装置のデータ読み出し方法、半導体記憶装置及び半導体記憶装置の制御装置
US6247151B1 (en) * 1998-06-30 2001-06-12 Intel Corporation Method and apparatus for verifying that data stored in a memory has not been corrupted
JP2000228094A (ja) * 1999-02-04 2000-08-15 Toshiba Corp 不揮発性半導体記憶装置
FR2790887B1 (fr) 1999-03-09 2003-01-03 Univ Joseph Fourier Circuit logique protege contre des perturbations transitoires
JP2003518287A (ja) 1999-12-23 2003-06-03 ジェネラル・インスツルメント・コーポレイション デュアルモードプロセッサ
JP3450814B2 (ja) * 2000-09-26 2003-09-29 松下電器産業株式会社 情報処理装置
FR2815197B1 (fr) * 2000-10-06 2003-01-03 St Microelectronics Sa Circuit asynchrone pour la detection et la correction de l'erreur induite et procede de mise en oeuvre

Also Published As

Publication number Publication date
RU2005129281A (ru) 2006-01-27
EP1604371A1 (de) 2005-12-14
DE602004001679T2 (de) 2007-08-02
KR100955285B1 (ko) 2010-04-30
JP2006520953A (ja) 2006-09-14
US7072229B2 (en) 2006-07-04
KR20060009236A (ko) 2006-01-31
WO2004084233A1 (en) 2004-09-30
US20060018171A1 (en) 2006-01-26
JP4279874B2 (ja) 2009-06-17
EP1604371B1 (de) 2006-07-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition