DE60210170D1 - Speichersystem - Google Patents

Speichersystem

Info

Publication number
DE60210170D1
DE60210170D1 DE60210170T DE60210170T DE60210170D1 DE 60210170 D1 DE60210170 D1 DE 60210170D1 DE 60210170 T DE60210170 T DE 60210170T DE 60210170 T DE60210170 T DE 60210170T DE 60210170 D1 DE60210170 D1 DE 60210170D1
Authority
DE
Germany
Prior art keywords
storage system
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60210170T
Other languages
English (en)
Other versions
DE60210170T2 (de
Inventor
Maksim Kuzmenka
Konstantin Korotkov
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE60210170D1 publication Critical patent/DE60210170D1/de
Publication of DE60210170T2 publication Critical patent/DE60210170T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE60210170T 2002-07-15 2002-07-15 Speichersystem Expired - Lifetime DE60210170T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02015608A EP1383052B1 (de) 2002-07-15 2002-07-15 Speichersystem

Publications (2)

Publication Number Publication Date
DE60210170D1 true DE60210170D1 (de) 2006-05-18
DE60210170T2 DE60210170T2 (de) 2006-11-02

Family

ID=29762617

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60210170T Expired - Lifetime DE60210170T2 (de) 2002-07-15 2002-07-15 Speichersystem

Country Status (3)

Country Link
US (1) US6856554B2 (de)
EP (1) EP1383052B1 (de)
DE (1) DE60210170T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002007201A (ja) * 2000-06-21 2002-01-11 Nec Corp メモリシステム、メモリインターフェース及びメモリチップ
DE10162583B4 (de) * 2001-12-19 2004-05-13 Infineon Technologies Ag Verzweigte Befehls/Adressbus-Architektur für registrierte Speichereinheiten
US7428644B2 (en) * 2003-06-20 2008-09-23 Micron Technology, Inc. System and method for selective memory module power management
US7389364B2 (en) * 2003-07-22 2008-06-17 Micron Technology, Inc. Apparatus and method for direct memory access in a hub-based memory system
US20050050237A1 (en) * 2003-08-28 2005-03-03 Jeddeloh Joseph M. Memory module and method having on-board data search capabilities and processor-based system using such memory modules
US7194593B2 (en) * 2003-09-18 2007-03-20 Micron Technology, Inc. Memory hub with integrated non-volatile memory
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US20050289284A1 (en) * 2004-06-24 2005-12-29 Ge Chang High speed memory modules
US20110047318A1 (en) * 2009-08-19 2011-02-24 Dmitroca Robert W Reducing capacitive load in a large memory array

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6028781A (en) * 1996-12-19 2000-02-22 Texas Instruments Incorporated Selectable integrated circuit assembly and method of operation
US5903167A (en) * 1997-03-05 1999-05-11 Sony Corporation High speed CMOS bus transmitter and receiver
JP3832947B2 (ja) * 1997-11-14 2006-10-11 富士通株式会社 データ転送メモリ装置
US5953215A (en) * 1997-12-01 1999-09-14 Karabatsos; Chris Apparatus and method for improving computer memory speed and capacity
US6349051B1 (en) * 1998-01-29 2002-02-19 Micron Technology, Inc. High speed data bus
JPH11353228A (ja) * 1998-06-10 1999-12-24 Mitsubishi Electric Corp メモリモジュールシステム
WO2000075796A1 (en) * 1999-06-08 2000-12-14 Koninklijke Philips Electronics N.V. Isolated high-speed communication bus
JP4675442B2 (ja) * 1999-11-02 2011-04-20 富士通セミコンダクター株式会社 メモリデバイス
JP2001297587A (ja) * 2000-04-18 2001-10-26 Mitsubishi Electric Corp 半導体記憶装置
US6934785B2 (en) * 2000-12-22 2005-08-23 Micron Technology, Inc. High speed interface with looped bus

Also Published As

Publication number Publication date
EP1383052A1 (de) 2004-01-21
EP1383052B1 (de) 2006-03-29
US6856554B2 (en) 2005-02-15
US20040008545A1 (en) 2004-01-15
DE60210170T2 (de) 2006-11-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE