DE60127260D1 - Verfahren zur verminderung kapazitiver last in einem flash-speicher-zeilendekodierer zur genauen spannungsregulierung von wort- und auswahlleitungen - Google Patents

Verfahren zur verminderung kapazitiver last in einem flash-speicher-zeilendekodierer zur genauen spannungsregulierung von wort- und auswahlleitungen

Info

Publication number
DE60127260D1
DE60127260D1 DE60127260T DE60127260T DE60127260D1 DE 60127260 D1 DE60127260 D1 DE 60127260D1 DE 60127260 T DE60127260 T DE 60127260T DE 60127260 T DE60127260 T DE 60127260T DE 60127260 D1 DE60127260 D1 DE 60127260D1
Authority
DE
Germany
Prior art keywords
capacitive loading
flash memory
well region
wordline
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60127260T
Other languages
English (en)
Other versions
DE60127260T2 (de
Inventor
Binh Q Le
Kazuhiro Kurihara
Pau-Ling Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spansion LLC
Original Assignee
Spansion LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion LLC filed Critical Spansion LLC
Publication of DE60127260D1 publication Critical patent/DE60127260D1/de
Application granted granted Critical
Publication of DE60127260T2 publication Critical patent/DE60127260T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits

Landscapes

  • Read Only Memory (AREA)
DE60127260T 2000-06-13 2001-06-04 Verfahren zur verminderung kapazitiver last in einem flash-speicher-zeilendekodierer zur genauen spannungsregulierung von wort- und auswahlleitungen Expired - Lifetime DE60127260T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US593303 1975-07-07
US09/593,303 US6208561B1 (en) 2000-06-13 2000-06-13 Method to reduce capacitive loading in flash memory X-decoder for accurate voltage control at wordlines and select lines
PCT/US2001/018081 WO2001097230A2 (en) 2000-06-13 2001-06-04 Method to reduce capacitive loading in flash memory x-decoder for accurate voltage control at wordlines and select lines

Publications (2)

Publication Number Publication Date
DE60127260D1 true DE60127260D1 (de) 2007-04-26
DE60127260T2 DE60127260T2 (de) 2007-12-20

Family

ID=24374212

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60127260T Expired - Lifetime DE60127260T2 (de) 2000-06-13 2001-06-04 Verfahren zur verminderung kapazitiver last in einem flash-speicher-zeilendekodierer zur genauen spannungsregulierung von wort- und auswahlleitungen

Country Status (11)

Country Link
US (1) US6208561B1 (de)
EP (1) EP1297534B1 (de)
JP (1) JP4737918B2 (de)
KR (1) KR100708915B1 (de)
CN (1) CN1264169C (de)
AT (1) ATE357046T1 (de)
AU (1) AU2001266701A1 (de)
BR (1) BR0111684A (de)
DE (1) DE60127260T2 (de)
TW (1) TW512352B (de)
WO (1) WO2001097230A2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100536613B1 (ko) * 2004-04-09 2005-12-14 삼성전자주식회사 프로그램 시간을 단축할 수 있는 노어형 플래시 메모리장치 및 그것의 프로그램 방법
US7525853B2 (en) * 2005-08-12 2009-04-28 Spansion Llc Semiconductor device and method for boosting word line
KR100672104B1 (ko) * 2005-10-28 2007-01-19 주식회사 하이닉스반도체 플래시 메모리 소자
JP6164048B2 (ja) * 2013-11-01 2017-07-19 セイコーエプソン株式会社 半導体記憶装置及びそれに用いられる回路装置
JP2017228325A (ja) 2016-06-20 2017-12-28 ウィンボンド エレクトロニクス コーポレーション 不揮発性半導体記憶装置
JP2019053799A (ja) * 2017-09-14 2019-04-04 東芝メモリ株式会社 半導体記憶装置
TWI686806B (zh) * 2019-02-13 2020-03-01 旺宏電子股份有限公司 記憶體裝置
JP7048794B1 (ja) 2021-05-06 2022-04-05 ウィンボンド エレクトロニクス コーポレーション 半導体装置および動作方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0521812A (ja) * 1991-07-16 1993-01-29 Toshiba Corp 不揮発性半導体メモリ
JP3441087B2 (ja) * 1991-12-25 2003-08-25 株式会社東芝 不揮発性半導体記憶装置
KR100211189B1 (ko) * 1994-11-29 1999-07-15 다니구찌 이찌로오, 기타오카 다카시 양/음 고전압발생전원의 출력전위 리셋회로
JPH09306187A (ja) * 1996-05-10 1997-11-28 Nec Corp 不揮発性半導体記憶装置
US5841696A (en) * 1997-03-05 1998-11-24 Advanced Micro Devices, Inc. Non-volatile memory enabling simultaneous reading and writing by time multiplexing a decode path
JP2964982B2 (ja) * 1997-04-01 1999-10-18 日本電気株式会社 不揮発性半導体記憶装置
JP2956645B2 (ja) * 1997-04-07 1999-10-04 日本電気株式会社 半導体装置
WO1999027537A1 (en) * 1997-11-21 1999-06-03 Macronix International Co., Ltd. On chip voltage generation for low power integrated circuits
JP3705925B2 (ja) * 1998-04-13 2005-10-12 株式会社ルネサステクノロジ Ｍｏｓ集積回路および不揮発性メモリ
ITTO980497A1 (it) * 1998-06-05 1999-12-05 St Microelectronics Srl Decodificatore di riga per un dispositivo di memoria a bassa tensione di alimentazione.

Also Published As

Publication number Publication date
TW512352B (en) 2002-12-01
AU2001266701A1 (en) 2001-12-24
BR0111684A (pt) 2003-07-01
US6208561B1 (en) 2001-03-27
WO2001097230A3 (en) 2002-05-30
KR100708915B1 (ko) 2007-04-18
CN1264169C (zh) 2006-07-12
KR20030014265A (ko) 2003-02-15
ATE357046T1 (de) 2007-04-15
WO2001097230A2 (en) 2001-12-20
DE60127260T2 (de) 2007-12-20
EP1297534B1 (de) 2007-03-14
EP1297534A2 (de) 2003-04-02
JP4737918B2 (ja) 2011-08-03
CN1439161A (zh) 2003-08-27
JP2004503898A (ja) 2004-02-05

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