DE60035115D1 - Architketur, verfahren und schaltungen für speichervorrichtungen mit geringer leistungsaufnahme - Google Patents

Architketur, verfahren und schaltungen für speichervorrichtungen mit geringer leistungsaufnahme

Info

Publication number
DE60035115D1
DE60035115D1 DE60035115T DE60035115T DE60035115D1 DE 60035115 D1 DE60035115 D1 DE 60035115D1 DE 60035115 T DE60035115 T DE 60035115T DE 60035115 T DE60035115 T DE 60035115T DE 60035115 D1 DE60035115 D1 DE 60035115D1
Authority
DE
Germany
Prior art keywords
architecture
circuits
approximately
providing
power consumption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60035115T
Other languages
English (en)
Other versions
DE60035115T2 (de
Inventor
Keith A Ford
Iulian C Gradinariu
Bogdan I Georgescu
Sean B Mulholland
John J Silver
Danny L Rose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
S Aqua Semiconductor LLC
Original Assignee
Cypress Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cypress Semiconductor Corp filed Critical Cypress Semiconductor Corp
Publication of DE60035115D1 publication Critical patent/DE60035115D1/de
Application granted granted Critical
Publication of DE60035115T2 publication Critical patent/DE60035115T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Electronic Switches (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Power Sources (AREA)
DE60035115T 1999-09-17 2000-09-15 Architketur, verfahren und schaltungen für speichervorrichtungen mit geringer leistungsaufnahme Expired - Lifetime DE60035115T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US398735 1982-07-15
US09/398,735 US6163495A (en) 1999-09-17 1999-09-17 Architecture, method(s) and circuitry for low power memories
PCT/US2000/025374 WO2001020610A1 (en) 1999-09-17 2000-09-15 Architecture, method(s) and circuitry for low power memories

Publications (2)

Publication Number Publication Date
DE60035115D1 true DE60035115D1 (de) 2007-07-19
DE60035115T2 DE60035115T2 (de) 2008-01-31

Family

ID=23576591

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60035115T Expired - Lifetime DE60035115T2 (de) 1999-09-17 2000-09-15 Architketur, verfahren und schaltungen für speichervorrichtungen mit geringer leistungsaufnahme

Country Status (10)

Country Link
US (3) US6163495A (de)
EP (1) EP1214713B1 (de)
JP (1) JP5105680B2 (de)
KR (1) KR100765157B1 (de)
AT (1) ATE364228T1 (de)
AU (1) AU7492100A (de)
CA (1) CA2384862A1 (de)
DE (1) DE60035115T2 (de)
IL (2) IL148680A0 (de)
WO (1) WO2001020610A1 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6163495A (en) 1999-09-17 2000-12-19 Cypress Semiconductor Corp. Architecture, method(s) and circuitry for low power memories
US6530040B1 (en) * 1999-09-22 2003-03-04 Cypress Semiconductor Corp. Parallel test in asynchronous memory with single-ended output path
US8164362B2 (en) * 2000-02-02 2012-04-24 Broadcom Corporation Single-ended sense amplifier with sample-and-hold reference
US6535025B2 (en) 2000-02-02 2003-03-18 Broadcom Corp. Sense amplifier with offset cancellation and charge-share limited swing drivers
US6411557B2 (en) 2000-02-02 2002-06-25 Broadcom Corporation Memory architecture with single-port cell and dual-port (read and write) functionality
US6414899B2 (en) * 2000-02-02 2002-07-02 Broadcom Corporation Limited swing driver circuit
US6603712B2 (en) 2000-02-02 2003-08-05 Broadcom Corporation High precision delay measurement circuit
US6724681B2 (en) * 2000-02-02 2004-04-20 Broadcom Corporation Asynchronously-resettable decoder with redundancy
US6417697B2 (en) 2000-02-02 2002-07-09 Broadcom Corporation Circuit technique for high speed low power data transfer bus
US6492844B2 (en) 2000-02-02 2002-12-10 Broadcom Corporation Single-ended sense amplifier with sample-and-hold reference
US6745354B2 (en) 2000-02-02 2004-06-01 Broadcom Corporation Memory redundancy implementation
US6611465B2 (en) 2000-02-02 2003-08-26 Broadcom Corporation Diffusion replica delay circuit
US7173867B2 (en) * 2001-02-02 2007-02-06 Broadcom Corporation Memory redundancy circuit techniques
US6937538B2 (en) * 2000-02-02 2005-08-30 Broadcom Corporation Asynchronously resettable decoder for a semiconductor memory
US6714467B2 (en) * 2002-03-19 2004-03-30 Broadcom Corporation Block redundancy implementation in heirarchical RAM's
KR100625294B1 (ko) * 2004-10-30 2006-09-18 주식회사 하이닉스반도체 전원 공급 제어 회로 및 전원 공급 회로의 제어 방법
JP4917767B2 (ja) * 2005-07-01 2012-04-18 パナソニック株式会社 半導体記憶装置
KR100700160B1 (ko) * 2005-08-23 2007-03-28 삼성전자주식회사 반도체 메모리 장치 및 반도체 메모리 장치의 워드라인활성화 방법
DE102007007566B4 (de) * 2007-02-15 2012-08-23 Qimonda Ag Halbleiter-Bauelement-System, Speichermodul und Verfahren zum Betreiben eines Halbleiter-Bauelement-Systems
US20110261613A1 (en) * 2010-04-27 2011-10-27 Mosaid Technologies Incorporated Phase change memory array blocks with alternate selection
US8526227B2 (en) 2010-06-23 2013-09-03 Mosaid Technologies Incorporated Phase change memory word line driver
US10316152B2 (en) 2014-01-10 2019-06-11 CommScope Connectivity Belgium BVBA Thermoplastic gel compositions and their methods of making

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01178193A (ja) * 1988-01-07 1989-07-14 Toshiba Corp 半導体記憶装置
JPH01294295A (ja) * 1988-05-20 1989-11-28 Fujitsu Ltd パーシャル・ランダム・アクセス・メモリ
JP2547615B2 (ja) * 1988-06-16 1996-10-23 三菱電機株式会社 読出専用半導体記憶装置および半導体記憶装置
JP2805761B2 (ja) * 1988-08-29 1998-09-30 日本電気株式会社 スタティックメモリ
US5349206A (en) * 1988-11-10 1994-09-20 Seiko Epson Corporation Integrated memory circuit with high density load elements
JPH02247892A (ja) * 1989-03-20 1990-10-03 Fujitsu Ltd ダイナミックランダムアクセスメモリ
US4985639A (en) * 1989-07-07 1991-01-15 Hewlett-Packard Company Logic edge timing generation
US5126973A (en) * 1990-02-14 1992-06-30 Texas Instruments Incorporated Redundancy scheme for eliminating defects in a memory device
US5270975A (en) * 1990-03-29 1993-12-14 Texas Instruments Incorporated Memory device having a non-uniform redundancy decoder arrangement
JPH0474384A (ja) * 1990-07-17 1992-03-09 Toshiba Corp 半導体集積回路装置
JP2519593B2 (ja) * 1990-10-24 1996-07-31 三菱電機株式会社 半導体記憶装置
JPH06103599B2 (ja) * 1990-11-16 1994-12-14 三菱電機株式会社 半導体集積回路装置
JPH04182988A (ja) * 1990-11-16 1992-06-30 Hitachi Ltd 半導体記憶装置
JPH0563525A (ja) * 1991-08-29 1993-03-12 Nec Corp パルス幅可変回路
JPH05151797A (ja) * 1991-11-26 1993-06-18 Nec Ic Microcomput Syst Ltd 半導体集積回路
JP3605122B2 (ja) * 1991-12-13 2004-12-22 テキサス インスツルメンツ インコーポレイテツド 補償回路と遅延を補償する方法
JPH05307899A (ja) * 1992-04-24 1993-11-19 Samsung Electron Co Ltd 半導体メモリ装置
US5264745A (en) * 1992-08-28 1993-11-23 Advanced Micro Devices, Inc. Recovering phase and data from distorted duty cycles caused by ECL-to-CMOS translator
KR950004855B1 (ko) * 1992-10-30 1995-05-15 현대전자산업 주식회사 반도체 메모리 소자의 어드레스 전이 검출 회로
US5323360A (en) 1993-05-03 1994-06-21 Motorola Inc. Localized ATD summation for a memory
DE69432634D1 (de) * 1993-08-13 2003-06-12 Irvine Sensors Corp Ic-stapel als ersatz für einzelnen ic
US5696463A (en) * 1993-11-02 1997-12-09 Hyundai Electronics Industries Co., Ltd. Address transition detecting circuit which generates constant pulse width signal
US5555529A (en) * 1993-12-28 1996-09-10 Intel Corporation Power saving architecture for a cache memory
JPH08172169A (ja) * 1994-12-16 1996-07-02 Toshiba Microelectron Corp 半導体記憶装置
JPH08273363A (ja) * 1995-03-30 1996-10-18 Nec Corp 半導体記憶装置
AU1752297A (en) * 1996-01-24 1997-08-20 Cypress Semiconductor Corp. Interdigitated memory array
EP0814481B1 (de) * 1996-06-18 2002-03-20 STMicroelectronics S.r.l. Nichtflüchtige Speicheranordnung mit niedriger Versorgungsspannung und Spannungserhöher
US5872464A (en) * 1996-08-12 1999-02-16 Cypress Semiconductor Corp. Input buffer with stabilized trip points
US5968190A (en) 1996-10-31 1999-10-19 Cypress Semiconductor Corp. Redundancy method and circuit for self-repairing memory arrays
KR100240418B1 (ko) * 1996-12-31 2000-03-02 윤종용 반도체 독출 전용 메모리 및 그의 독출 방법
US5828614A (en) * 1997-04-07 1998-10-27 Cypress Semiconductor Corp. Memory cell sensing method and circuitry for bit line equalization
JPH11195766A (ja) * 1997-10-31 1999-07-21 Mitsubishi Electric Corp 半導体集積回路装置
US6118727A (en) 1998-03-10 2000-09-12 Cypress Semiconductor Corporation Semiconductor memory with interdigitated array having bit line pairs accessible from either of two sides of the array
US6378008B1 (en) 1998-11-25 2002-04-23 Cypress Semiconductor Corporation Output data path scheme in a memory device
US6323701B1 (en) 1998-12-28 2001-11-27 Cypress Semiconductor Corporation Scheme for reducing leakage current in an input buffer
US6163495A (en) * 1999-09-17 2000-12-19 Cypress Semiconductor Corp. Architecture, method(s) and circuitry for low power memories

Also Published As

Publication number Publication date
KR20020035142A (ko) 2002-05-09
US20020191470A1 (en) 2002-12-19
AU7492100A (en) 2001-04-17
US6674682B2 (en) 2004-01-06
CA2384862A1 (en) 2001-03-22
DE60035115T2 (de) 2008-01-31
EP1214713A4 (de) 2004-12-22
WO2001020610A1 (en) 2001-03-22
US6493283B1 (en) 2002-12-10
IL148680A (en) 2007-12-03
EP1214713B1 (de) 2007-06-06
ATE364228T1 (de) 2007-06-15
US6163495A (en) 2000-12-19
IL148680A0 (en) 2002-09-12
KR100765157B1 (ko) 2007-10-15
EP1214713A1 (de) 2002-06-19
JP5105680B2 (ja) 2012-12-26
JP2003509802A (ja) 2003-03-11

Similar Documents

Publication Publication Date Title
DE60035115D1 (de) Architketur, verfahren und schaltungen für speichervorrichtungen mit geringer leistungsaufnahme
ATE259545T1 (de) Halbleiter-schaltsstromvorrichtung mit betriebsverstärker und verfahren zur herstellung
ATE426898T1 (de) Mram-architektur fur niedrige stromaufnahme und hohe selektivitat
GB2367931B (en) Circuit and method for multiple match detection in content addressable memories
EP0725402A3 (de) Halbleiterspeicheranordnung
EP1225589A3 (de) Halbleiterspeicheranordnung mit einer Vielzahl von Moden für geringen Stromverbrauch
TW344133B (en) Semiconductor memory
EP0807935A3 (de) Gleichzeitiges Lese- und Schreibeverfahren von Daten in einem RAM-Speicher
TW326534B (en) Semiconductor memory device
KR870004449A (ko) Ram내의 데이타 라인 사전 충전
WO2004053881A3 (en) Source-biased memory cell array
EP0986066A3 (de) Ferroelektrischer Speicher und seine Testverfahren
KR950009725A (ko) 반도체 메모리 장치
TW200509131A (en) Semiconductor memory device
Shibata Current sense amplifiers for low-voltage memories
EP1361580A3 (de) Halbleieterspeicheranordnung und zugehöriges Steuerungsverfahren
EP0801397A3 (de) Verbesserungen für oder in Bezug auf Halbleiterspeicheranordnungen
WO2002095761A3 (en) Apparatus and method for memory storage cell leakage cancellation scheme
US6483739B2 (en) 4T memory with boost of stored voltage between standby and active
TW353180B (en) A method and apparatus for bit cell ground choking for improved memory write margin
JP2007531412A (ja) リーク電流低減方法
DE602004017664D1 (de) Statische Direktzugriffspeicherzelle (SRAM) und Speichereinheit die diese enthält mit extrem niedrigem Leistungsverbrauch
KR960025776A (ko) 셰어드 센스앰프 방식의 센스 램프로 소비되는 전력을 경감한 반도체 기억 장치
DE59800692D1 (de) Ansteuerschaltung für nichtflüchtige halbleiter-speicheranordnung
WO2002093581A3 (de) Magnetische speicheranordnung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: DOT ASSETS NO. 10 LLC,, WILMINGTON, DEL., US