DE4219927A1 - Anordnung von spannungsquelle- und erdungsleitungen einer halbleiterspeichereinrichtung - Google Patents

Anordnung von spannungsquelle- und erdungsleitungen einer halbleiterspeichereinrichtung

Info

Publication number
DE4219927A1
DE4219927A1 DE4219927A DE4219927A DE4219927A1 DE 4219927 A1 DE4219927 A1 DE 4219927A1 DE 4219927 A DE4219927 A DE 4219927A DE 4219927 A DE4219927 A DE 4219927A DE 4219927 A1 DE4219927 A1 DE 4219927A1
Authority
DE
Germany
Prior art keywords
voltage source
input
memory device
semiconductor memory
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE4219927A
Other languages
German (de)
English (en)
Inventor
Young-Ho Seo
Hyoung-Kyu Yim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE4219927A1 publication Critical patent/DE4219927A1/de
Ceased legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Layout of the interconnection structure
    • H01L23/5286Arrangements of power or ground buses
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211Design considerations for internal polarisation
    • H10D89/213Design considerations for internal polarisation in field-effect devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
DE4219927A 1991-06-19 1992-06-17 Anordnung von spannungsquelle- und erdungsleitungen einer halbleiterspeichereinrichtung Ceased DE4219927A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910010194A KR930001392A (ko) 1991-06-19 1991-06-19 반도체 메모리 장치의 전원 접지선 배선방법

Publications (1)

Publication Number Publication Date
DE4219927A1 true DE4219927A1 (de) 1992-12-24

Family

ID=19316015

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4219927A Ceased DE4219927A1 (de) 1991-06-19 1992-06-17 Anordnung von spannungsquelle- und erdungsleitungen einer halbleiterspeichereinrichtung

Country Status (7)

Country Link
JP (1) JPH0719851B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR930001392A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE4219927A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR2678109B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB2256968A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
IT (1) IT1258990B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
TW (1) TW245835B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100249166B1 (ko) * 1997-03-07 2000-03-15 김영환 이에스디(esd) 보호회로 및 그 제조방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5780828A (en) * 1980-11-07 1982-05-20 Hitachi Ltd Semiconductor integrated circuit device
JPS5922357A (ja) * 1982-07-28 1984-02-04 Toshiba Corp Cmos形半導体集積回路
JPH0693497B2 (ja) * 1986-07-30 1994-11-16 日本電気株式会社 相補型mis集積回路
GB2199695B (en) * 1987-01-06 1990-07-25 Samsung Semiconductor Inc Dynamic random access memory with selective well biasing
US5023689A (en) * 1987-03-18 1991-06-11 Nec Corporation Complementary integrated circuit device equipped with latch-up preventing means

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, Vol. 33, No. 12, Mai 1991, S. 439-441 *
JP 2-126652 A. In: PATENTS ABSTRACTS OF JAPAN, E-959, Vol. 14, No. 359, 3.8.90 *
JP 59-163 837 A. In: PATENTS ABSTRACTS OF JAPAN, E-291, Vol. 9/No. 15, 22.1.85 *

Also Published As

Publication number Publication date
KR930001392A (ko) 1993-01-16
JPH0719851B2 (ja) 1995-03-06
GB2256968A (en) 1992-12-23
ITMI921460A1 (it) 1993-12-12
IT1258990B (it) 1996-03-11
TW245835B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1995-04-21
FR2678109A1 (fr) 1992-12-24
FR2678109B1 (fr) 1994-01-21
JPH06112435A (ja) 1994-04-22
ITMI921460A0 (it) 1992-06-12
GB9212830D0 (en) 1992-07-29

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection