DE4107006C2 - - Google Patents

Info

Publication number
DE4107006C2
DE4107006C2 DE4107006A DE4107006A DE4107006C2 DE 4107006 C2 DE4107006 C2 DE 4107006C2 DE 4107006 A DE4107006 A DE 4107006A DE 4107006 A DE4107006 A DE 4107006A DE 4107006 C2 DE4107006 C2 DE 4107006C2
Authority
DE
Germany
Prior art keywords
etching
aluminum
mask
gas mixture
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE4107006A
Other languages
German (de)
English (en)
Other versions
DE4107006A1 (de
Inventor
Wolfgang E. Dipl.-Ing. 8043 Unterfoehring De Frank
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE4107006A priority Critical patent/DE4107006A1/de
Priority to FR9202157A priority patent/FR2673764B1/fr
Priority to EP19920103772 priority patent/EP0502523A3/de
Priority to US07/847,779 priority patent/US5277750A/en
Publication of DE4107006A1 publication Critical patent/DE4107006A1/de
Application granted granted Critical
Publication of DE4107006C2 publication Critical patent/DE4107006C2/de
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/02068Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Metallurgy (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE4107006A 1991-03-05 1991-03-05 Verfahren zum anisotropen trockenaetzen von aluminium bzw. aluminiumlegierungen enthaltenden leiterbahnebenen in integrierten halbleiterschaltungen Granted DE4107006A1 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE4107006A DE4107006A1 (de) 1991-03-05 1991-03-05 Verfahren zum anisotropen trockenaetzen von aluminium bzw. aluminiumlegierungen enthaltenden leiterbahnebenen in integrierten halbleiterschaltungen
FR9202157A FR2673764B1 (fr) 1991-03-05 1992-02-25 Procede pour realiser la corrosion anisotrope a sec de plans de voies conductrices, contenant de l'aluminium ou des alliages d'aluminium, dans des circuits integres a semiconducteurs.
EP19920103772 EP0502523A3 (en) 1991-03-05 1992-03-05 Method for anisotropic dry etching of aluminium as well as aluminium alloys containing path levels in integrated semiconductor circuits
US07/847,779 US5277750A (en) 1991-03-05 1992-03-05 Method for anisotropic dry etching of metallization layers, containing aluminum or aluminum alloys, in integrated semiconductor circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4107006A DE4107006A1 (de) 1991-03-05 1991-03-05 Verfahren zum anisotropen trockenaetzen von aluminium bzw. aluminiumlegierungen enthaltenden leiterbahnebenen in integrierten halbleiterschaltungen

Publications (2)

Publication Number Publication Date
DE4107006A1 DE4107006A1 (de) 1992-09-10
DE4107006C2 true DE4107006C2 (enrdf_load_stackoverflow) 1993-02-18

Family

ID=6426519

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4107006A Granted DE4107006A1 (de) 1991-03-05 1991-03-05 Verfahren zum anisotropen trockenaetzen von aluminium bzw. aluminiumlegierungen enthaltenden leiterbahnebenen in integrierten halbleiterschaltungen

Country Status (4)

Country Link
US (1) US5277750A (enrdf_load_stackoverflow)
EP (1) EP0502523A3 (enrdf_load_stackoverflow)
DE (1) DE4107006A1 (enrdf_load_stackoverflow)
FR (1) FR2673764B1 (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4317722A1 (de) * 1993-05-27 1994-12-01 Siemens Ag Verfahren zum anisotropen Ätzen einer aluminiumhaltigen Schicht

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US5387556A (en) * 1993-02-24 1995-02-07 Applied Materials, Inc. Etching aluminum and its alloys using HC1, C1-containing etchant and N.sub.2
US5607599A (en) * 1994-11-17 1997-03-04 Kabushiki Kaisha Toshiba Method of processing a magnetic thin film
US5591301A (en) * 1994-12-22 1997-01-07 Siemens Aktiengesellschaft Plasma etching method
US5651856A (en) * 1996-01-22 1997-07-29 Micron Technology, Inc. Selective etch process
US5843289A (en) * 1996-01-22 1998-12-01 Etex Corporation Surface modification of medical implants
KR980005793A (ko) * 1996-06-12 1998-03-30 김광호 반도체장치 제조공정의 플라즈마 식각 방법
US5849641A (en) * 1997-03-19 1998-12-15 Lam Research Corporation Methods and apparatus for etching a conductive layer to improve yield
JP3484332B2 (ja) * 1997-11-11 2004-01-06 Tdk株式会社 薄膜磁気ヘッドの製造方法
JP3790347B2 (ja) * 1997-11-26 2006-06-28 Tdk株式会社 薄膜磁気ヘッドの製造方法
TW505984B (en) 1997-12-12 2002-10-11 Applied Materials Inc Method of etching patterned layers useful as masking during subsequent etching or for damascene structures
US6143476A (en) * 1997-12-12 2000-11-07 Applied Materials Inc Method for high temperature etching of patterned layers using an organic mask stack
JP2985858B2 (ja) * 1997-12-19 1999-12-06 日本電気株式会社 エッチング方法
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US6268287B1 (en) * 1999-10-15 2001-07-31 Taiwan Semiconductor Manufacturing Company Polymerless metal hard mask etching
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JP2003068705A (ja) * 2001-08-23 2003-03-07 Hitachi Ltd 半導体素子の製造方法
DE10147791A1 (de) * 2001-09-27 2003-04-10 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines Halbleiterbauelements auf der Basis eines Nitrid-Verbindungshalbleiters
JP2003249575A (ja) * 2002-02-22 2003-09-05 Seiko Epson Corp 不揮発性記憶装置の製造方法
JP4865978B2 (ja) * 2002-02-28 2012-02-01 富士通セミコンダクター株式会社 半導体装置の製造方法
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4317722A1 (de) * 1993-05-27 1994-12-01 Siemens Ag Verfahren zum anisotropen Ätzen einer aluminiumhaltigen Schicht

Also Published As

Publication number Publication date
US5277750A (en) 1994-01-11
EP0502523A3 (en) 1992-11-19
DE4107006A1 (de) 1992-09-10
FR2673764A1 (fr) 1992-09-11
FR2673764B1 (fr) 1995-09-29
EP0502523A2 (de) 1992-09-09

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