DE69331862T2 - Trockenätzverfahren eines Polyzids ohne Verwendung von FCKW-Gasen - Google Patents
Trockenätzverfahren eines Polyzids ohne Verwendung von FCKW-GasenInfo
- Publication number
- DE69331862T2 DE69331862T2 DE69331862T DE69331862T DE69331862T2 DE 69331862 T2 DE69331862 T2 DE 69331862T2 DE 69331862 T DE69331862 T DE 69331862T DE 69331862 T DE69331862 T DE 69331862T DE 69331862 T2 DE69331862 T2 DE 69331862T2
- Authority
- DE
- Germany
- Prior art keywords
- polyzide
- etching process
- dry etching
- cfc gases
- cfc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000001312 dry etching Methods 0.000 title 1
- 239000007789 gas Substances 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- ing And Chemical Polishing (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP05910692A JP3198586B2 (ja) | 1992-02-14 | 1992-02-14 | ドライエッチング方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69331862D1 DE69331862D1 (de) | 2002-06-06 |
DE69331862T2 true DE69331862T2 (de) | 2002-10-31 |
Family
ID=13103735
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69331862T Expired - Fee Related DE69331862T2 (de) | 1992-02-14 | 1993-02-11 | Trockenätzverfahren eines Polyzids ohne Verwendung von FCKW-Gasen |
Country Status (5)
Country | Link |
---|---|
US (1) | US5391244A (de) |
EP (1) | EP0555858B1 (de) |
JP (1) | JP3198586B2 (de) |
KR (1) | KR100255402B1 (de) |
DE (1) | DE69331862T2 (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2650178B2 (ja) * | 1992-12-05 | 1997-09-03 | ヤマハ株式会社 | ドライエッチング方法及び装置 |
JPH0786244A (ja) * | 1993-09-13 | 1995-03-31 | Sony Corp | ドライエッチング方法 |
US5674782A (en) * | 1993-12-31 | 1997-10-07 | Samsung Electronics Co., Ltd. | Method for efficiently removing by-products produced in dry-etching |
GB2297864B (en) * | 1994-12-12 | 1998-11-11 | Japan Res Dev Corp | Method for etching semiconductor crystals |
US5554563A (en) * | 1995-04-04 | 1996-09-10 | Taiwan Semiconductor Manufacturing Company | In situ hot bake treatment that prevents precipitate formation after a contact layer etch back step |
US5882535A (en) * | 1997-02-04 | 1999-03-16 | Micron Technology, Inc. | Method for forming a hole in a semiconductor device |
JPH10223608A (ja) * | 1997-02-04 | 1998-08-21 | Sony Corp | 半導体装置の製造方法 |
KR100673142B1 (ko) * | 2000-05-29 | 2007-01-22 | 주식회사 하이닉스반도체 | 게이트 전극 형성 방법 |
JP2003195082A (ja) * | 2001-12-26 | 2003-07-09 | Hitachi Cable Ltd | 溝部の形成方法および光導波路素子の製造方法 |
US6855643B2 (en) * | 2002-07-12 | 2005-02-15 | Padmapani C. Nallan | Method for fabricating a gate structure |
JP2009021584A (ja) * | 2007-06-27 | 2009-01-29 | Applied Materials Inc | 高k材料ゲート構造の高温エッチング方法 |
US9533332B2 (en) | 2011-10-06 | 2017-01-03 | Applied Materials, Inc. | Methods for in-situ chamber clean utilized in an etching processing chamber |
US8932947B1 (en) | 2013-07-23 | 2015-01-13 | Applied Materials, Inc. | Methods for forming a round bottom silicon trench recess for semiconductor applications |
US9214377B2 (en) | 2013-10-31 | 2015-12-15 | Applied Materials, Inc. | Methods for silicon recess structures in a substrate by utilizing a doping layer |
CN110571129B (zh) * | 2018-06-05 | 2022-08-02 | 上海新微技术研发中心有限公司 | 一种导电金属氧化物的加工方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4465552A (en) * | 1983-08-11 | 1984-08-14 | Allied Corporation | Method of selectively etching silicon dioxide with SF6 /nitriding component gas |
JPS6050923A (ja) * | 1983-08-31 | 1985-03-22 | Hitachi Ltd | プラズマ表面処理方法 |
JPS61220432A (ja) * | 1985-03-27 | 1986-09-30 | Hitachi Ltd | エツチング方法 |
JPS648628A (en) * | 1987-06-30 | 1989-01-12 | Kyocera Corp | Gas etching |
JPS6432627A (en) * | 1987-07-29 | 1989-02-02 | Hitachi Ltd | Low-temperature dry etching method |
JPH01166539A (ja) * | 1987-12-23 | 1989-06-30 | Hitachi Ltd | 低温ドライエツチング方法および低温ドライエツチング装置 |
JPH0817170B2 (ja) * | 1988-07-28 | 1996-02-21 | 富士通株式会社 | 半導体装置のエッチング方法 |
JP2681117B2 (ja) * | 1989-04-26 | 1997-11-26 | 康夫 南日 | 化合物半導体表面の安定化方法 |
JPH0336723A (ja) * | 1989-07-04 | 1991-02-18 | Fujitsu Ltd | 半導体装置の製造方法及び電子サイクロトロン共鳴エッチング装置 |
JP2591209B2 (ja) * | 1990-01-22 | 1997-03-19 | ソニー株式会社 | ドライエッチング方法 |
JP2964605B2 (ja) * | 1990-10-04 | 1999-10-18 | ソニー株式会社 | ドライエッチング方法 |
JP3220992B2 (ja) * | 1991-01-22 | 2001-10-22 | ソニー株式会社 | ドライエッチング方法 |
JP3371143B2 (ja) * | 1991-06-03 | 2003-01-27 | ソニー株式会社 | ドライエッチング方法 |
-
1992
- 1992-02-14 JP JP05910692A patent/JP3198586B2/ja not_active Expired - Fee Related
-
1993
- 1993-02-04 US US08/013,325 patent/US5391244A/en not_active Expired - Fee Related
- 1993-02-11 DE DE69331862T patent/DE69331862T2/de not_active Expired - Fee Related
- 1993-02-11 EP EP93102170A patent/EP0555858B1/de not_active Expired - Lifetime
- 1993-02-12 KR KR1019930001891A patent/KR100255402B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100255402B1 (ko) | 2000-06-01 |
JPH05226304A (ja) | 1993-09-03 |
EP0555858A2 (de) | 1993-08-18 |
EP0555858A3 (de) | 1995-02-22 |
US5391244A (en) | 1995-02-21 |
DE69331862D1 (de) | 2002-06-06 |
KR930018664A (ko) | 1993-09-22 |
JP3198586B2 (ja) | 2001-08-13 |
EP0555858B1 (de) | 2002-05-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |