DE4106155A1 - Dynamischer schreib-lesespeicher und verfahren zum betreiben eines solchen - Google Patents

Dynamischer schreib-lesespeicher und verfahren zum betreiben eines solchen

Info

Publication number
DE4106155A1
DE4106155A1 DE4106155A DE4106155A DE4106155A1 DE 4106155 A1 DE4106155 A1 DE 4106155A1 DE 4106155 A DE4106155 A DE 4106155A DE 4106155 A DE4106155 A DE 4106155A DE 4106155 A1 DE4106155 A1 DE 4106155A1
Authority
DE
Germany
Prior art keywords
write data
write
potential level
internal write
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE4106155A
Other languages
German (de)
English (en)
Other versions
DE4106155C2 (cg-RX-API-DMAC7.html
Inventor
Erfinder Wird Nachtraeglich Benannt Der
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE4106155A1 publication Critical patent/DE4106155A1/de
Application granted granted Critical
Publication of DE4106155C2 publication Critical patent/DE4106155C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
DE4106155A 1990-02-28 1991-02-27 Dynamischer schreib-lesespeicher und verfahren zum betreiben eines solchen Granted DE4106155A1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP5039890 1990-02-28
JP5039790 1990-02-28
JP5039690 1990-02-28
JP2318754A JP2604277B2 (ja) 1990-02-28 1990-11-22 ダイナミック・ランダム・アクセス・メモリ

Publications (2)

Publication Number Publication Date
DE4106155A1 true DE4106155A1 (de) 1991-09-05
DE4106155C2 DE4106155C2 (cg-RX-API-DMAC7.html) 1993-07-29

Family

ID=27462489

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4106155A Granted DE4106155A1 (de) 1990-02-28 1991-02-27 Dynamischer schreib-lesespeicher und verfahren zum betreiben eines solchen

Country Status (4)

Country Link
US (1) US5103423A (cg-RX-API-DMAC7.html)
JP (1) JP2604277B2 (cg-RX-API-DMAC7.html)
KR (1) KR940008293B1 (cg-RX-API-DMAC7.html)
DE (1) DE4106155A1 (cg-RX-API-DMAC7.html)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5289432A (en) * 1991-04-24 1994-02-22 International Business Machines Corporation Dual-port static random access memory cell
US5708609A (en) * 1996-09-05 1998-01-13 Winbond Electronics Corp. Semiconductor memory device with dataline undershoot detection and reduced read access time
JPH11126491A (ja) * 1997-08-20 1999-05-11 Fujitsu Ltd 半導体記憶装置
US6266178B1 (en) 1998-12-28 2001-07-24 Texas Instruments Incorporated Guardring DRAM cell
US6779141B1 (en) * 2000-06-08 2004-08-17 Sun Microsystems, Inc. System and method for implementing memory testing in a SRAM unit
JP4415467B2 (ja) * 2000-09-06 2010-02-17 株式会社日立製作所 画像表示装置
US8648403B2 (en) * 2006-04-21 2014-02-11 International Business Machines Corporation Dynamic memory cell structures
US9087565B2 (en) 2012-11-20 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pre-charging a data line
WO2018012120A1 (ja) * 2016-07-13 2018-01-18 富士電機株式会社 パワーモジュール

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4853896A (en) * 1986-06-10 1989-08-01 Nec Corporation Write driver circuit of semiconductor memory device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01178193A (ja) * 1988-01-07 1989-07-14 Toshiba Corp 半導体記憶装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4853896A (en) * 1986-06-10 1989-08-01 Nec Corporation Write driver circuit of semiconductor memory device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Electronics, 17.11.82, S. 155-159 *

Also Published As

Publication number Publication date
KR940008293B1 (ko) 1994-09-10
KR920000074A (ko) 1992-01-10
JP2604277B2 (ja) 1997-04-30
DE4106155C2 (cg-RX-API-DMAC7.html) 1993-07-29
JPH03263684A (ja) 1991-11-25
US5103423A (en) 1992-04-07

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Representative=s name: PRUFER & PARTNER GBR, 81545 MUENCHEN

8339 Ceased/non-payment of the annual fee