DE3912750C2 - - Google Patents

Info

Publication number
DE3912750C2
DE3912750C2 DE3912750A DE3912750A DE3912750C2 DE 3912750 C2 DE3912750 C2 DE 3912750C2 DE 3912750 A DE3912750 A DE 3912750A DE 3912750 A DE3912750 A DE 3912750A DE 3912750 C2 DE3912750 C2 DE 3912750C2
Authority
DE
Germany
Prior art keywords
signal
binary signal
phase difference
phase
pll circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3912750A
Other languages
German (de)
English (en)
Other versions
DE3912750A1 (de
Inventor
Kazunori Sanada
Jyoji Kobe Hyogo Jp Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3912750A1 publication Critical patent/DE3912750A1/de
Application granted granted Critical
Publication of DE3912750C2 publication Critical patent/DE3912750C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE3912750A 1988-04-25 1989-04-19 Pll-schaltung Granted DE3912750A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63102012A JP2554705B2 (ja) 1988-04-25 1988-04-25 位相同期回路

Publications (2)

Publication Number Publication Date
DE3912750A1 DE3912750A1 (de) 1989-11-09
DE3912750C2 true DE3912750C2 (enExample) 1992-11-26

Family

ID=14315851

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3912750A Granted DE3912750A1 (de) 1988-04-25 1989-04-19 Pll-schaltung

Country Status (4)

Country Link
US (1) US5005141A (enExample)
JP (1) JP2554705B2 (enExample)
KR (1) KR920006439B1 (enExample)
DE (1) DE3912750A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0410712A (ja) * 1990-04-27 1992-01-14 Shin Kobe Electric Mach Co Ltd 位相同期制御回路
US5396109A (en) * 1991-09-26 1995-03-07 Olympus Optical Co., Ltd. Bit clock regenerating circuit and data regenerating method
NO925012L (no) * 1991-12-27 1993-06-28 Mitsubishi Electric Corp Demodulator med forsinket deteksjon
US5365182A (en) * 1993-06-22 1994-11-15 Motorola, Inc. Method and apparatus for low power clock generation for high speed applications

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS582493B2 (ja) * 1975-01-14 1983-01-17 日本電気株式会社 デイジタルイソウドウキカイロ
JPS5580061A (en) * 1978-12-12 1980-06-16 Advantest Corp Frequency measuring apparatus
YU40393B (en) * 1980-06-09 1985-12-31 Iskra Pll-based clock extractor with code control with a minimized phase jitter and extended locking range
GB2147123B (en) * 1983-08-04 1987-06-03 Canon Kk Motor control device
SE8403225D0 (sv) * 1984-06-15 1984-06-15 Asea Ab Metod for fastlast sampling av en periodisk signal
US4723216A (en) * 1985-08-01 1988-02-02 General Electric Company Digital frequency-locked loop for use with staggered sampling systems
US4715000A (en) * 1985-08-06 1987-12-22 General Electric Company Digital phase-locked loop and frequency measuring device
US4808884A (en) * 1985-12-02 1989-02-28 Western Digital Corporation High order digital phase-locked loop system
US4807146A (en) * 1986-02-19 1989-02-21 Louisiana State University Digital lock-in amplifier
JPS62247622A (ja) * 1986-04-18 1987-10-28 Sanyo Electric Co Ltd 位相同期回路
US4672299A (en) * 1986-05-23 1987-06-09 American Telephone And Telegraph Co. Clock control circuit for phase control
US4752748A (en) * 1987-04-16 1988-06-21 Amdahl Corporation Intelligent phase-locked loop
US4847870A (en) * 1987-11-25 1989-07-11 Siemens Transmission Systems, Inc. High resolution digital phase-lock loop circuit
US4864253A (en) * 1987-12-22 1989-09-05 Siemens Aktiengesellschaft Phase locked loop wherein phase comparing and filtering are performed by microprocessor

Also Published As

Publication number Publication date
JPH01272323A (ja) 1989-10-31
DE3912750A1 (de) 1989-11-09
KR890016774A (ko) 1989-11-30
KR920006439B1 (ko) 1992-08-06
JP2554705B2 (ja) 1996-11-13
US5005141A (en) 1991-04-02

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee