YU40393B - Pll-based clock extractor with code control with a minimized phase jitter and extended locking range - Google Patents

Pll-based clock extractor with code control with a minimized phase jitter and extended locking range

Info

Publication number
YU40393B
YU40393B YU153080A YU153080A YU40393B YU 40393 B YU40393 B YU 40393B YU 153080 A YU153080 A YU 153080A YU 153080 A YU153080 A YU 153080A YU 40393 B YU40393 B YU 40393B
Authority
YU
Yugoslavia
Prior art keywords
pll
code control
phase jitter
locking range
based clock
Prior art date
Application number
YU153080A
Other versions
YU153080A (en
Inventor
A Irsic
Original Assignee
Iskra
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Iskra filed Critical Iskra
Priority to YU153080A priority Critical patent/YU40393B/en
Priority to DE19813122811 priority patent/DE3122811A1/en
Publication of YU153080A publication Critical patent/YU153080A/en
Publication of YU40393B publication Critical patent/YU40393B/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
YU153080A 1980-06-09 1980-06-09 Pll-based clock extractor with code control with a minimized phase jitter and extended locking range YU40393B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
YU153080A YU40393B (en) 1980-06-09 1980-06-09 Pll-based clock extractor with code control with a minimized phase jitter and extended locking range
DE19813122811 DE3122811A1 (en) 1980-06-09 1981-06-09 Clock extractor with code control based on a phase-locked loop with minimised phase jitter and increased capture range

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
YU153080A YU40393B (en) 1980-06-09 1980-06-09 Pll-based clock extractor with code control with a minimized phase jitter and extended locking range

Publications (2)

Publication Number Publication Date
YU153080A YU153080A (en) 1982-08-31
YU40393B true YU40393B (en) 1985-12-31

Family

ID=25554528

Family Applications (1)

Application Number Title Priority Date Filing Date
YU153080A YU40393B (en) 1980-06-09 1980-06-09 Pll-based clock extractor with code control with a minimized phase jitter and extended locking range

Country Status (2)

Country Link
DE (1) DE3122811A1 (en)
YU (1) YU40393B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3407450A1 (en) * 1984-02-29 1985-08-29 Siemens AG, 1000 Berlin und 8000 München Pulse regeneration circuit
DE3544675A1 (en) * 1985-12-18 1987-06-25 Philips Patentverwaltung CIRCUIT ARRANGEMENT FOR CONTROLLING A FREQUENCY-DEPENDENT OSCILLATOR
JP2554705B2 (en) * 1988-04-25 1996-11-13 三菱電機株式会社 Phase synchronization circuit

Also Published As

Publication number Publication date
YU153080A (en) 1982-08-31
DE3122811A1 (en) 1982-04-08

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