DE3882977D1 - Verfahren und anordnung zur implementierung von mehrverriegelungsanzeigen in einem multiprozessordatenverarbeitungssystem. - Google Patents

Verfahren und anordnung zur implementierung von mehrverriegelungsanzeigen in einem multiprozessordatenverarbeitungssystem.

Info

Publication number
DE3882977D1
DE3882977D1 DE8888904314T DE3882977T DE3882977D1 DE 3882977 D1 DE3882977 D1 DE 3882977D1 DE 8888904314 T DE8888904314 T DE 8888904314T DE 3882977 T DE3882977 T DE 3882977T DE 3882977 D1 DE3882977 D1 DE 3882977D1
Authority
DE
Germany
Prior art keywords
arrangement
data processing
processing system
multiprocessor data
implementing multi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888904314T
Other languages
English (en)
Other versions
DE3882977T2 (de
Inventor
Richard Gillett
Douglas Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of DE3882977D1 publication Critical patent/DE3882977D1/de
Application granted granted Critical
Publication of DE3882977T2 publication Critical patent/DE3882977T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Vehicle Body Suspensions (AREA)
  • Hardware Redundancy (AREA)
  • Control By Computers (AREA)
DE88904314T 1987-05-01 1988-04-25 Verfahren und anordnung zur implementierung von mehrverriegelungsanzeigen in einem multiprozessordatenverarbeitungssystem. Expired - Fee Related DE3882977T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/044,466 US4949239A (en) 1987-05-01 1987-05-01 System for implementing multiple lock indicators on synchronous pended bus in multiprocessor computer system
PCT/US1988/001299 WO1988008584A1 (en) 1987-05-01 1988-04-25 Method and apparatus for implementing multiple lock indicators in a multiprocessor computer system

Publications (2)

Publication Number Publication Date
DE3882977D1 true DE3882977D1 (de) 1993-09-09
DE3882977T2 DE3882977T2 (de) 1994-03-24

Family

ID=21932544

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88904314T Expired - Fee Related DE3882977T2 (de) 1987-05-01 1988-04-25 Verfahren und anordnung zur implementierung von mehrverriegelungsanzeigen in einem multiprozessordatenverarbeitungssystem.

Country Status (8)

Country Link
US (1) US4949239A (de)
EP (1) EP0344216B1 (de)
JP (1) JPH0642236B2 (de)
KR (1) KR910007750B1 (de)
AU (1) AU600830B2 (de)
CA (1) CA1304828C (de)
DE (1) DE3882977T2 (de)
WO (1) WO1988008584A1 (de)

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US5182809A (en) * 1989-05-31 1993-01-26 International Business Machines Corporation Dual bus microcomputer system with programmable control of lock function
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US5499356A (en) * 1989-12-29 1996-03-12 Cray Research, Inc. Method and apparatus for a multiprocessor resource lockout instruction
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US5276847A (en) * 1990-02-14 1994-01-04 Intel Corporation Method for locking and unlocking a computer address
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US5430860A (en) * 1991-09-17 1995-07-04 International Business Machines Inc. Mechanism for efficiently releasing memory lock, after allowing completion of current atomic sequence
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US5574862A (en) * 1993-04-14 1996-11-12 Radius Inc. Multiprocessing system with distributed input/output management
JP3360933B2 (ja) * 1994-06-01 2003-01-07 富士通株式会社 情報処理システムにおける記憶制御方法および記憶制御装置
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US5701422A (en) * 1995-12-13 1997-12-23 Ncr Corporation Method for ensuring cycle ordering requirements within a hierarchical bus system including split-transaction buses
US5872980A (en) * 1996-01-25 1999-02-16 International Business Machines Corporation Semaphore access control buffer and method for accelerated semaphore operations
DE69733011T2 (de) 1997-06-27 2005-09-29 Bull S.A. Schnittstellenbrücke zwischen einem Systembus und einem lokalen Bus zur Steuerung wenigstens eines Slave-Gerätes, wie ein ROM-Speicher
US6421751B1 (en) * 1998-11-23 2002-07-16 Advanced Micro Devices, Inc. Detecting a no-tags-free condition in a computer system having multiple outstanding transactions
US6611891B1 (en) 1998-11-23 2003-08-26 Advanced Micro Devices, Inc. Computer resource configuration mechanism across a multi-pipe communication link
US6397225B1 (en) * 1998-12-23 2002-05-28 Advanced Micro Devices, Inc. Messaging system with protocol independent message format
US6529983B1 (en) 1999-11-03 2003-03-04 Cisco Technology, Inc. Group and virtual locking mechanism for inter processor synchronization
US6681341B1 (en) 1999-11-03 2004-01-20 Cisco Technology, Inc. Processor isolation method for integrated multi-processor systems
US6892237B1 (en) 2000-03-28 2005-05-10 Cisco Technology, Inc. Method and apparatus for high-speed parsing of network messages
US6505269B1 (en) 2000-05-16 2003-01-07 Cisco Technology, Inc. Dynamic addressing mapping to eliminate memory resource contention in a symmetric multiprocessor system
US6922745B2 (en) * 2002-05-02 2005-07-26 Intel Corporation Method and apparatus for handling locks
JP4576323B2 (ja) * 2004-12-10 2010-11-04 富士通株式会社 データ転送装置およびデータ転送方法
US7315910B2 (en) * 2005-06-16 2008-01-01 Oracle International Corporation Techniques for handling lock-related inconsistencies
US8994533B2 (en) * 2006-11-30 2015-03-31 Patent Navigation, Inc. Conditional RFID
US8001328B2 (en) * 2008-01-29 2011-08-16 International Business Machines Corporation Method and process for expediting the return of line exclusivity to a given processor through enhanced inter-node communications
US9560134B1 (en) * 2012-06-27 2017-01-31 Netapp, Inc. Storage array side write locking
US20170111286A1 (en) * 2015-10-15 2017-04-20 Kabushiki Kaisha Toshiba Storage system that includes a plurality of routing circuits and a plurality of node modules connected thereto
CN113821470B (zh) * 2020-06-19 2024-09-06 杭州中天微系统有限公司 总线设备、嵌入式系统和片上系统

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Also Published As

Publication number Publication date
KR890702145A (ko) 1989-12-23
AU1716888A (en) 1988-12-02
KR910007750B1 (ko) 1991-09-30
AU600830B2 (en) 1990-08-23
DE3882977T2 (de) 1994-03-24
CA1304828C (en) 1992-07-07
JPH02500783A (ja) 1990-03-15
WO1988008584A1 (en) 1988-11-03
JPH0642236B2 (ja) 1994-06-01
EP0344216B1 (de) 1993-08-04
EP0344216A1 (de) 1989-12-06
US4949239A (en) 1990-08-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee