DE69323790D1 - Verfahren und Vorrichtung für mehreren ausstehende Operationen in einem cachespeicherkohärenten Multiprozessorsystem - Google Patents

Verfahren und Vorrichtung für mehreren ausstehende Operationen in einem cachespeicherkohärenten Multiprozessorsystem

Info

Publication number
DE69323790D1
DE69323790D1 DE69323790T DE69323790T DE69323790D1 DE 69323790 D1 DE69323790 D1 DE 69323790D1 DE 69323790 T DE69323790 T DE 69323790T DE 69323790 T DE69323790 T DE 69323790T DE 69323790 D1 DE69323790 D1 DE 69323790D1
Authority
DE
Germany
Prior art keywords
multiprocessor system
cache coherent
pending operations
multiple pending
coherent multiprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69323790T
Other languages
English (en)
Other versions
DE69323790T2 (de
Inventor
Jung-Herng Chang
Curt Berg
Jorge Cruz-Rios
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of DE69323790D1 publication Critical patent/DE69323790D1/de
Application granted granted Critical
Publication of DE69323790T2 publication Critical patent/DE69323790T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69323790T 1992-04-29 1993-04-19 Verfahren und Vorrichtung für mehreren ausstehende Operationen in einem cachespeicherkohärenten Multiprozessorsystem Expired - Fee Related DE69323790T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US87635992A 1992-04-29 1992-04-29

Publications (2)

Publication Number Publication Date
DE69323790D1 true DE69323790D1 (de) 1999-04-15
DE69323790T2 DE69323790T2 (de) 1999-10-07

Family

ID=25367523

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69323790T Expired - Fee Related DE69323790T2 (de) 1992-04-29 1993-04-19 Verfahren und Vorrichtung für mehreren ausstehende Operationen in einem cachespeicherkohärenten Multiprozessorsystem

Country Status (5)

Country Link
US (1) US5377345A (de)
EP (1) EP0568231B1 (de)
JP (1) JPH0744458A (de)
KR (1) KR100274327B1 (de)
DE (1) DE69323790T2 (de)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06149669A (ja) * 1992-11-04 1994-05-31 Fujitsu Ltd キャッシュデータ転送方式およびキャッシュデータ転送装置
JP3490742B2 (ja) * 1993-09-08 2004-01-26 松下電器産業株式会社 メモリ管理装置
KR970010368B1 (ko) * 1994-01-18 1997-06-25 삼성전자 주식회사 캐시라인 리프레이스장치 및 방법
CA2148028A1 (en) * 1994-05-25 1995-11-26 Deborah L. Mcguinness Knowledge base management system with dependency information for procedural tests
JP3360933B2 (ja) * 1994-06-01 2003-01-07 富士通株式会社 情報処理システムにおける記憶制御方法および記憶制御装置
US5787465A (en) * 1994-07-01 1998-07-28 Digital Equipment Corporation Destination indexed miss status holding registers
US5717895A (en) * 1994-12-01 1998-02-10 Cray Research, Inc. Associative scalar data cache with write-through capabilities for a vector processor
US5642494A (en) * 1994-12-21 1997-06-24 Intel Corporation Cache memory with reduced request-blocking
US5860127A (en) * 1995-06-01 1999-01-12 Hitachi, Ltd. Cache memory employing dynamically controlled data array start timing and a microcomputer using the same
US5761712A (en) * 1995-06-07 1998-06-02 Advanced Micro Devices Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array
US5778434A (en) * 1995-06-07 1998-07-07 Seiko Epson Corporation System and method for processing multiple requests and out of order returns
JP2964926B2 (ja) * 1995-08-29 1999-10-18 富士ゼロックス株式会社 データベース管理装置及び方法
KR100387576B1 (ko) * 1995-12-29 2003-09-22 엘지엔시스(주) 멀티프로세서시스템의캐쉬응집프로토콜처리방법
US5822755A (en) * 1996-01-25 1998-10-13 International Business Machines Corporation Dual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cache
US5937431A (en) * 1996-07-12 1999-08-10 Samsung Electronics Co., Ltd. Multi- node, multi-level cache- only memory architecture with relaxed inclusion
JP2919376B2 (ja) * 1996-08-23 1999-07-12 日本電気アイシーマイコンシステム株式会社 読出し専用記憶媒体の読出し方法
US5860158A (en) * 1996-11-15 1999-01-12 Samsung Electronics Company, Ltd. Cache control unit with a cache request transaction-oriented protocol
US6052762A (en) * 1996-12-02 2000-04-18 International Business Machines Corp. Method and apparatus for reducing system snoop latency
US6085288A (en) * 1997-04-14 2000-07-04 International Business Machines Corporation Dual cache directories with respective queue independently executing its content and allowing staggered write operations
US6785888B1 (en) * 1997-08-29 2004-08-31 International Business Machines Corporation Memory allocator for a multiprocessor computer system
US6625694B2 (en) * 1998-05-08 2003-09-23 Fujitsu Ltd. System and method for allocating a directory entry for use in multiprocessor-node data processing systems
US6237067B1 (en) 1998-08-31 2001-05-22 International Business Machines Corporation System and method for handling storage consistency conflict
US6449697B1 (en) 1999-04-23 2002-09-10 International Business Machines Corporation Prestaging data into cache in preparation for data transfer operations
AUPQ486599A0 (en) * 1999-12-23 2000-02-03 Zentronix Pty Ltd A method of storing and retrieving miniaturised data
US6564229B1 (en) * 2000-06-08 2003-05-13 International Business Machines Corporation System and method for pausing and resuming move/copy operations
US6732234B1 (en) * 2000-08-07 2004-05-04 Broadcom Corporation Direct access mode for a cache
US6748492B1 (en) 2000-08-07 2004-06-08 Broadcom Corporation Deterministic setting of replacement policy in a cache through way selection
US6848024B1 (en) * 2000-08-07 2005-01-25 Broadcom Corporation Programmably disabling one or more cache entries
US6748495B2 (en) 2001-05-15 2004-06-08 Broadcom Corporation Random generator
US6832279B1 (en) * 2001-05-17 2004-12-14 Cisco Systems, Inc. Apparatus and technique for maintaining order among requests directed to a same address on an external bus of an intermediate network node
JP2002368850A (ja) * 2001-06-05 2002-12-20 Sony Corp 携帯無線端末装置
KR100617663B1 (ko) * 2001-09-14 2006-08-28 썬 마이크로시스템즈, 인코포레이티드 캐시 메모리 내 태그 액세스 및 데이터 액세스의 분리방법 및 장치
US7000081B2 (en) * 2002-02-12 2006-02-14 Ip-First, Llc Write back and invalidate mechanism for multiple cache lines
US7266587B2 (en) * 2002-05-15 2007-09-04 Broadcom Corporation System having interfaces, switch, and memory bridge for CC-NUMA operation
JP2010033480A (ja) * 2008-07-31 2010-02-12 Sony Corp キャッシュメモリおよびキャッシュメモリ制御装置
US8504774B2 (en) 2010-10-13 2013-08-06 Microsoft Corporation Dynamic cache configuration using separate read and write caches
US9311251B2 (en) 2012-08-27 2016-04-12 Apple Inc. System cache with sticky allocation
US20140089600A1 (en) * 2012-09-27 2014-03-27 Apple Inc. System cache with data pending state
WO2014174578A1 (ja) * 2013-04-22 2014-10-30 株式会社日立製作所 エッジサーバ及び記憶制御方法
CN104331352B (zh) * 2014-11-19 2018-03-09 浪潮(北京)电子信息产业有限公司 cache一致性芯片地址带外读取检测方法及装置
US10558462B2 (en) * 2018-05-23 2020-02-11 Arm Limited Apparatus and method for storing source operands for operations
CN111104166B (zh) * 2019-12-13 2022-09-06 北京新忆科技有限公司 寄存器的写入方法和写入装置
CN116049031B (zh) * 2023-02-28 2024-08-30 海光信息技术股份有限公司 数据处理方法、装置、电子设备和存储介质

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE280954C (de) *
JPS55146682A (en) * 1979-05-01 1980-11-15 Nec Corp Data transfer system
US4315310A (en) * 1979-09-28 1982-02-09 Intel Corporation Input/output data processing system
US4370710A (en) * 1980-08-26 1983-01-25 Control Data Corporation Cache memory organization utilizing miss information holding registers to prevent lockup from cache misses
US4493026A (en) * 1982-05-26 1985-01-08 International Business Machines Corporation Set associative sector cache
US4794521A (en) * 1985-07-22 1988-12-27 Alliant Computer Systems Corporation Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
DE3862488D1 (de) * 1987-02-16 1991-05-29 Siemens Ag Verfahren zur steuerung des datenaustausches zwischen verarbeitungseinheiten und einem speichersystem mit cachespeicher in datenverarbeitungsanlagen, sowie ein entsprechend arbeitender cachespeicher.
US5025366A (en) * 1988-01-20 1991-06-18 Advanced Micro Devices, Inc. Organization of an integrated cache unit for flexible usage in cache system design
US4977498A (en) * 1988-04-01 1990-12-11 Digital Equipment Corporation Data processing system having a data memory interlock coherency scheme
US5025365A (en) * 1988-11-14 1991-06-18 Unisys Corporation Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors
US5018063A (en) * 1988-12-05 1991-05-21 International Business Machines Corporation Method for reducing cross-interrogate delays in a multiprocessor system
US5197146A (en) * 1989-06-21 1993-03-23 Hewlett-Packard Company Method for maintaining cache coherence in a multiprocessor computer system
US5230070A (en) * 1989-09-08 1993-07-20 International Business Machines Corporation Access authorization table for multi-processor caches
US5136700A (en) * 1989-12-22 1992-08-04 Digital Equipment Corporation Apparatus and method for reducing interference in two-level cache memories
JPH061463B2 (ja) * 1990-01-16 1994-01-05 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチプロセッサ・システムおよびそのプライベート・キャッシュ制御方法
US5163140A (en) * 1990-02-26 1992-11-10 Nexgen Microsystems Two-level branch prediction cache
US5210845A (en) * 1990-11-28 1993-05-11 Intel Corporation Controller for two-way set associative cache
US5228134A (en) * 1991-06-04 1993-07-13 Intel Corporation Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus

Also Published As

Publication number Publication date
EP0568231A1 (de) 1993-11-03
US5377345A (en) 1994-12-27
EP0568231B1 (de) 1999-03-10
KR930022222A (ko) 1993-11-23
KR100274327B1 (ko) 2000-12-15
DE69323790T2 (de) 1999-10-07
JPH0744458A (ja) 1995-02-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee