DE19782177T1 - Verfahren und Einrichtung zur Durchführung von TLB-Shootdown-Operationen in einem Multiprozessorsystem - Google Patents

Verfahren und Einrichtung zur Durchführung von TLB-Shootdown-Operationen in einem Multiprozessorsystem

Info

Publication number
DE19782177T1
DE19782177T1 DE19782177T DE19782177T DE19782177T1 DE 19782177 T1 DE19782177 T1 DE 19782177T1 DE 19782177 T DE19782177 T DE 19782177T DE 19782177 T DE19782177 T DE 19782177T DE 19782177 T1 DE19782177 T1 DE 19782177T1
Authority
DE
Germany
Prior art keywords
operations
multiprocessor system
tlb shootdown
performing tlb
shootdown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19782177T
Other languages
English (en)
Other versions
DE19782177B4 (de
Inventor
William S Wu
Stephen S Pawlowski
Peter D Macwilliams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE19782177T1 publication Critical patent/DE19782177T1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/682—Multiprocessor TLB consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE19782177T 1996-12-19 1997-12-01 Verfahren und Einrichtung zur Durchführung von TLB-Shootdown-Operationen in einem Multiprozessorsystem Withdrawn DE19782177T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/770,733 US5906001A (en) 1996-12-19 1996-12-19 Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines
PCT/US1997/021744 WO1998027493A1 (en) 1996-12-19 1997-12-01 Method and apparatus for performing tlb shootdown operations in a multiprocessor system

Publications (1)

Publication Number Publication Date
DE19782177T1 true DE19782177T1 (de) 1999-11-25

Family

ID=25089515

Family Applications (2)

Application Number Title Priority Date Filing Date
DE19782177A Expired - Lifetime DE19782177B4 (de) 1996-12-19 1997-12-01 Verfahren zur Durchführung von TLB-Shootdown-Operationen in einem Multiprozessorsystem
DE19782177T Withdrawn DE19782177T1 (de) 1996-12-19 1997-12-01 Verfahren und Einrichtung zur Durchführung von TLB-Shootdown-Operationen in einem Multiprozessorsystem

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE19782177A Expired - Lifetime DE19782177B4 (de) 1996-12-19 1997-12-01 Verfahren zur Durchführung von TLB-Shootdown-Operationen in einem Multiprozessorsystem

Country Status (6)

Country Link
US (1) US5906001A (de)
AU (1) AU5687898A (de)
DE (2) DE19782177B4 (de)
GB (1) GB2335769B (de)
HK (1) HK1023194A1 (de)
WO (1) WO1998027493A1 (de)

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US6094708A (en) * 1997-05-06 2000-07-25 Cisco Technology, Inc. Secondary cache write-through blocking mechanism
US6668314B1 (en) * 1997-06-24 2003-12-23 Hewlett-Packard Development Company, L.P. Virtual memory translation control by TLB purge monitoring
US6115385A (en) 1998-03-11 2000-09-05 Cisco Technology, Inc. Method and system for subnetting in a switched IP network
US6119204A (en) * 1998-06-30 2000-09-12 International Business Machines Corporation Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization
US6785274B2 (en) 1998-10-07 2004-08-31 Cisco Technology, Inc. Efficient network multicast switching apparatus and methods
US6490671B1 (en) * 1999-05-28 2002-12-03 Oracle Corporation System for efficiently maintaining translation lockaside buffer consistency in a multi-threaded, multi-processor virtual memory system
US7509391B1 (en) * 1999-11-23 2009-03-24 Texas Instruments Incorporated Unified memory management system for multi processor heterogeneous architecture
US6741258B1 (en) * 2000-01-04 2004-05-25 Advanced Micro Devices, Inc. Distributed translation look-aside buffers for graphics address remapping table
US6560664B1 (en) * 2000-02-18 2003-05-06 Hewlett Packard Development Company, L.P. Method and apparatus for translation lookaside buffers to access a common hardware page walker
US6604185B1 (en) * 2000-07-20 2003-08-05 Silicon Graphics, Inc. Distribution of address-translation-purge requests to multiple processors
US6931510B1 (en) * 2000-07-31 2005-08-16 Sun Microsystems, Inc. Method and system for translation lookaside buffer coherence in multiprocessor systems
US6633967B1 (en) * 2000-08-31 2003-10-14 Hewlett-Packard Development Company, L.P. Coherent translation look-aside buffer
US7069413B1 (en) 2003-01-29 2006-06-27 Vmware, Inc. Method and system for performing virtual to physical address translations in a virtual machine monitor
US7617378B2 (en) * 2003-04-28 2009-11-10 International Business Machines Corporation Multiprocessor system with retry-less TLBI protocol
US7073043B2 (en) * 2003-04-28 2006-07-04 International Business Machines Corporation Multiprocessor system supporting multiple outstanding TLBI operations per partition
US7188229B2 (en) * 2004-01-17 2007-03-06 Sun Microsystems, Inc. Method and apparatus for memory management in a multi-processor computer system
US7562179B2 (en) * 2004-07-30 2009-07-14 Intel Corporation Maintaining processor resources during architectural events
US7281116B2 (en) * 2004-07-30 2007-10-09 Hewlett-Packard Development Company, L.P. Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes
DE102004062287A1 (de) * 2004-12-23 2006-07-13 Fujitsu Siemens Computers Gmbh Verfahren zur Aktualisierung von Einträgen von Adressumsetzpuffern in einem Mehrprozessor-Computersystem
US7454590B2 (en) * 2005-09-09 2008-11-18 Sun Microsystems, Inc. Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor cores
US7383415B2 (en) * 2005-09-09 2008-06-03 Sun Microsystems, Inc. Hardware demapping of TLBs shared by multiple threads
US7631147B2 (en) * 2006-12-06 2009-12-08 Microsoft Corporation Efficient flushing of translation lookaside buffers in a multiprocessor environment
US8412911B2 (en) * 2009-06-29 2013-04-02 Oracle America, Inc. System and method to invalidate obsolete address translations
US8938588B2 (en) 2010-12-16 2015-01-20 International Business Machines Corporation Ensuring forward progress of token-required cache operations in a shared cache
US8595464B2 (en) 2011-07-14 2013-11-26 Oracle International Corporation Dynamic sizing of translation lookaside buffer for power reduction
US9684606B2 (en) * 2014-11-14 2017-06-20 Cavium, Inc. Translation lookaside buffer invalidation suppression
US9665505B2 (en) 2014-11-14 2017-05-30 Cavium, Inc. Managing buffered communication between sockets
US9501425B2 (en) 2014-11-14 2016-11-22 Cavium, Inc. Translation lookaside buffer management
US9697137B2 (en) * 2014-11-14 2017-07-04 Cavium, Inc. Filtering translation lookaside buffer invalidations
US9910776B2 (en) 2014-11-14 2018-03-06 Cavium, Inc. Instruction ordering for in-progress operations
US9870328B2 (en) 2014-11-14 2018-01-16 Cavium, Inc. Managing buffered communication between cores
US9740629B2 (en) * 2014-12-19 2017-08-22 International Business Machines Corporation Tracking memory accesses when invalidating effective address to real address translations
US9779028B1 (en) 2016-04-01 2017-10-03 Cavium, Inc. Managing translation invalidation
GB2551226A (en) * 2016-06-08 2017-12-13 Google Inc TLB shootdowns for low overhead
US10540292B2 (en) * 2016-06-08 2020-01-21 Google Llc TLB shootdowns for low overhead
US10540291B2 (en) * 2017-05-10 2020-01-21 Intel Corporation Tracking and managing translation lookaside buffers
US10740239B2 (en) * 2018-12-11 2020-08-11 International Business Machines Corporation Translation entry invalidation in a multithreaded data processing system

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US5235684A (en) * 1988-06-30 1993-08-10 Wang Laboratories, Inc. System bus having multiplexed command/id and data
US5307477A (en) * 1989-12-01 1994-04-26 Mips Computer Systems, Inc. Two-level cache memory system
US5317705A (en) * 1990-10-24 1994-05-31 International Business Machines Corporation Apparatus and method for TLB purge reduction in a multi-level machine system
US5555420A (en) * 1990-12-21 1996-09-10 Intel Corporation Multiprocessor programmable interrupt controller system with separate interrupt bus and bus retry management
US5497480A (en) * 1990-12-31 1996-03-05 Sun Microsystems, Inc. Broadcast demap for deallocating memory pages in a multiprocessor system
US5574936A (en) * 1992-01-02 1996-11-12 Amdahl Corporation Access control mechanism controlling access to and logical purging of access register translation lookaside buffer (ALB) in a computer system
EP0585117A1 (de) * 1992-08-26 1994-03-02 Cyrix Corporation Verfahren und System zur Aufrechterhaltung der Cachespeicherübereinstimmung in einem Multimasterrechnersystem
US5437017A (en) * 1992-10-09 1995-07-25 International Business Machines Corporation Method and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing system
JPH0784883A (ja) * 1993-09-17 1995-03-31 Hitachi Ltd 仮想計算機システムのアドレス変換バッファパージ方法

Also Published As

Publication number Publication date
WO1998027493A1 (en) 1998-06-25
GB2335769B (en) 2002-01-23
GB2335769A (en) 1999-09-29
AU5687898A (en) 1998-07-15
DE19782177B4 (de) 2008-06-26
HK1023194A1 (en) 2000-09-01
US5906001A (en) 1999-05-18
GB9914075D0 (en) 1999-08-18

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20130702