DE3878065D1 - Testanordnung und -verfahren fuer integrierte schaltungen, womit das bestimmen von oberflaechenschichteffekten moeglich wird. - Google Patents

Testanordnung und -verfahren fuer integrierte schaltungen, womit das bestimmen von oberflaechenschichteffekten moeglich wird.

Info

Publication number
DE3878065D1
DE3878065D1 DE8888420237T DE3878065T DE3878065D1 DE 3878065 D1 DE3878065 D1 DE 3878065D1 DE 8888420237 T DE8888420237 T DE 8888420237T DE 3878065 T DE3878065 T DE 3878065T DE 3878065 D1 DE3878065 D1 DE 3878065D1
Authority
DE
Germany
Prior art keywords
surface layer
integrated circuits
test arrangement
layer effects
determines surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888420237T
Other languages
English (en)
Other versions
DE3878065T2 (de
Inventor
Andre Juge
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Publication of DE3878065D1 publication Critical patent/DE3878065D1/de
Application granted granted Critical
Publication of DE3878065T2 publication Critical patent/DE3878065T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
DE8888420237T 1987-07-07 1988-07-06 Testanordnung und -verfahren fuer integrierte schaltungen, womit das bestimmen von oberflaechenschichteffekten moeglich wird. Expired - Fee Related DE3878065T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8709903A FR2618021B1 (fr) 1987-07-07 1987-07-07 Structure et procede de test pour circuit integre permettant la determination des effets de surface de couches

Publications (2)

Publication Number Publication Date
DE3878065D1 true DE3878065D1 (de) 1993-03-18
DE3878065T2 DE3878065T2 (de) 1993-09-09

Family

ID=9353103

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888420237T Expired - Fee Related DE3878065T2 (de) 1987-07-07 1988-07-06 Testanordnung und -verfahren fuer integrierte schaltungen, womit das bestimmen von oberflaechenschichteffekten moeglich wird.

Country Status (6)

Country Link
US (1) US4906921A (de)
EP (1) EP0299887B1 (de)
JP (1) JPH0191430A (de)
KR (1) KR890003011A (de)
DE (1) DE3878065T2 (de)
FR (1) FR2618021B1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2886176B2 (ja) * 1989-03-23 1999-04-26 三菱電機株式会社 埋め込みチャネルの物性特性測定法
US5196787A (en) * 1989-10-19 1993-03-23 Texas Instruments Incorporated Test circuit for screening parts
US5059897A (en) * 1989-12-07 1991-10-22 Texas Instruments Incorporated Method and apparatus for testing passive substrates for integrated circuit mounting
US5196802A (en) * 1990-04-23 1993-03-23 The United States Of America As Represented By The Secretary Of The Navy Method and apparatus for characterizing the quality of electrically thin semiconductor films
JP3017871B2 (ja) * 1991-01-02 2000-03-13 テキサス インスツルメンツ インコーポレイテツド Ｉｃデバイスに対するチップ上のバラツキ検知回路
US5239270A (en) * 1992-02-24 1993-08-24 National Semiconductor Corporation Wafer level reliability contact test structure and method
US5600578A (en) * 1993-08-02 1997-02-04 Advanced Micro Devices, Inc. Test method for predicting hot-carrier induced leakage over time in short-channel IGFETs and products designed in accordance with test results
US5548224A (en) * 1995-01-20 1996-08-20 Vlsi Technology, Inc Method and apparatus for wafer level prediction of thin oxide reliability
KR100397675B1 (ko) * 1998-12-16 2004-02-14 제일모직주식회사 내열도가 우수한 열가소성 수지 조성물
US6144040A (en) * 1999-01-22 2000-11-07 Lucent Technologies Inc. Van der pauw structure to measure the resistivity of a doped area under diffusion areas and gate structures
KR100663347B1 (ko) * 2004-12-21 2007-01-02 삼성전자주식회사 중첩도 측정마크를 갖는 반도체소자 및 그 형성방법
DE102009006482B4 (de) * 2009-01-28 2013-05-02 Atlanta Antriebssysteme E. Seidenspinner Gmbh & Co. Kg Getriebe mit Gegenlager

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3974443A (en) * 1975-01-02 1976-08-10 International Business Machines Corporation Conductive line width and resistivity measuring system
US4467400A (en) * 1981-01-16 1984-08-21 Burroughs Corporation Wafer scale integrated circuit
US4479088A (en) * 1981-01-16 1984-10-23 Burroughs Corporation Wafer including test lead connected to ground for testing networks thereon
US4486705A (en) * 1981-01-16 1984-12-04 Burroughs Corporation Method of testing networks on a wafer having grounding points on its periphery
GB2173037A (en) * 1985-03-29 1986-10-01 Philips Electronic Associated Semiconductor devices employing conductivity modulation
US4672314A (en) * 1985-04-12 1987-06-09 Rca Corporation Comprehensive semiconductor test structure

Also Published As

Publication number Publication date
EP0299887B1 (de) 1993-02-03
KR890003011A (ko) 1989-04-12
JPH0191430A (ja) 1989-04-11
US4906921A (en) 1990-03-06
FR2618021A1 (fr) 1989-01-13
EP0299887A1 (de) 1989-01-18
DE3878065T2 (de) 1993-09-09
FR2618021B1 (fr) 1990-01-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee