DE3868457D1 - Statische ram-halbleiterspeicheranordnung. - Google Patents

Statische ram-halbleiterspeicheranordnung.

Info

Publication number
DE3868457D1
DE3868457D1 DE8888113070T DE3868457T DE3868457D1 DE 3868457 D1 DE3868457 D1 DE 3868457D1 DE 8888113070 T DE8888113070 T DE 8888113070T DE 3868457 T DE3868457 T DE 3868457T DE 3868457 D1 DE3868457 D1 DE 3868457D1
Authority
DE
Germany
Prior art keywords
static ram
semiconductor arrangement
ram semiconductor
arrangement
static
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8888113070T
Other languages
English (en)
Inventor
Takayuki Ootani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3868457D1 publication Critical patent/DE3868457D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
DE8888113070T 1987-08-13 1988-08-11 Statische ram-halbleiterspeicheranordnung. Expired - Lifetime DE3868457D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62202389A JPS6446288A (en) 1987-08-13 1987-08-13 Semiconductor memory device

Publications (1)

Publication Number Publication Date
DE3868457D1 true DE3868457D1 (de) 1992-03-26

Family

ID=16456684

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888113070T Expired - Lifetime DE3868457D1 (de) 1987-08-13 1988-08-11 Statische ram-halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US4933905A (de)
EP (1) EP0303971B1 (de)
JP (1) JPS6446288A (de)
KR (1) KR910003389B1 (de)
DE (1) DE3868457D1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0762955B2 (ja) * 1989-05-15 1995-07-05 株式会社東芝 ダイナミック型ランダムアクセスメモリ
US5155703A (en) * 1990-07-06 1992-10-13 Motorola, Inc. Bicmos bit line load for a memory with improved reliability
KR100208142B1 (ko) * 1990-09-26 1999-07-15 가나이 쓰도무 반도체 메모리
JPH04360095A (ja) * 1991-06-06 1992-12-14 Nec Corp 半導体記憶回路
US5226007A (en) * 1991-08-14 1993-07-06 Vlsi Technology, Inc. Automatic shutoff for memory load device during write operation
JP3057836B2 (ja) * 1991-08-19 2000-07-04 日本電気株式会社 半導体記憶装置
JP2762826B2 (ja) * 1992-03-09 1998-06-04 日本電気株式会社 半導体メモリ
JP2780621B2 (ja) * 1993-12-27 1998-07-30 日本電気株式会社 半導体記憶装置
US5471188A (en) * 1994-10-07 1995-11-28 International Business Machines Corporation Fast comparator circuit
JP3449676B2 (ja) * 1996-10-03 2003-09-22 シャープ株式会社 半導体記憶装置のビット線プリチャージ回路
KR100298030B1 (ko) * 1998-03-27 2001-10-25 다니구찌 이찌로오, 기타오카 다카시 저전원전압하에서고속으로동작하는스태틱형반도체기억장치
US8588004B2 (en) 2012-04-12 2013-11-19 Lsi Corporation Memory device having multi-port memory cell with expandable port configuration

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4195356A (en) * 1978-11-16 1980-03-25 Electronic Memories And Magnetics Corporation Sense line termination circuit for semiconductor memory systems
US4202045A (en) * 1979-03-05 1980-05-06 Motorola, Inc. Write circuit for a read/write memory
JPS5847792B2 (ja) * 1979-07-26 1983-10-25 富士通株式会社 ビット線制御回路
JPS592997B2 (ja) * 1980-05-22 1984-01-21 富士通株式会社 スタテイツクメモリ
JPS6027114B2 (ja) * 1980-07-24 1985-06-27 日本電気株式会社 メモリ装置
JPH0770222B2 (ja) * 1984-06-04 1995-07-31 株式会社日立製作所 Ｍｏｓスタテイツク型ｒａｍ
JPS6154096A (ja) * 1984-08-24 1986-03-18 Hitachi Ltd 半導体記憶装置
US4730279A (en) * 1985-03-30 1988-03-08 Kabushiki Kaisha Toshiba Static semiconductor memory device
JPS61237290A (ja) * 1985-04-12 1986-10-22 Sony Corp ビツト線駆動回路
JPS63166090A (ja) * 1986-12-26 1988-07-09 Toshiba Corp スタティック型メモリ
US4802129A (en) * 1987-12-03 1989-01-31 Motorola, Inc. RAM with dual precharge circuit and write recovery circuitry

Also Published As

Publication number Publication date
KR890004333A (ko) 1989-04-21
US4933905A (en) 1990-06-12
EP0303971A2 (de) 1989-02-22
EP0303971B1 (de) 1992-02-19
EP0303971A3 (en) 1989-08-23
JPS6446288A (en) 1989-02-20
KR910003389B1 (ko) 1991-05-28

Similar Documents

Publication Publication Date Title
DE3481957D1 (de) Halbleiteranordnung.
DE3583302D1 (de) Halbleiteranordnung.
DE3850855T2 (de) Halbleitervorrichtung.
DE3584799D1 (de) Halbleitervorrichtung.
DE3582653D1 (de) Halbleiteranordnung.
FI873581A0 (fi) Fast stoedanordning.
DE3667879D1 (de) Halbleiteranordnung.
DE3581370D1 (de) Halbleitervorrichtung.
DE3878320D1 (de) Statischer ram-speicher.
DE3889354D1 (de) Halbleiteranordnung.
DE3771241D1 (de) Dynamischer ram.
DE3586568T2 (de) Halbleitereinrichtung.
DE3868457D1 (de) Statische ram-halbleiterspeicheranordnung.
DE3787137T2 (de) Halbleiteranordnung.
DE3773663D1 (de) Statischer halbleiterspeicher.
FI871781A0 (fi) Anordning foer provtagning ur substans innehaollande fast aemne.
DE3773276D1 (de) Transistoranordnung.
DE68910327D1 (de) Halbleiteranordnung.
DE3861543D1 (de) Knickstab-anordnung.
DE3871823D1 (de) Halbleiterspeicheranordnung.
FI883435A (fi) Styrsystem foer fluider under tryck.
DE3781607D1 (de) Statische ram-speicheranordnungen.
DE3784777T2 (de) Halbleiteranordnung.
IT8422333A0 (it) Dispositivo di caricamento.
FI860896A0 (fi) Anordning foer att skilja material fraon varandra.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)