DE3853351D1 - Siliciumcarbidsperre zwischen einem Siliciumsubstrat und einer Metallschicht. - Google Patents

Siliciumcarbidsperre zwischen einem Siliciumsubstrat und einer Metallschicht.

Info

Publication number
DE3853351D1
DE3853351D1 DE3853351T DE3853351T DE3853351D1 DE 3853351 D1 DE3853351 D1 DE 3853351D1 DE 3853351 T DE3853351 T DE 3853351T DE 3853351 T DE3853351 T DE 3853351T DE 3853351 D1 DE3853351 D1 DE 3853351D1
Authority
DE
Germany
Prior art keywords
metal layer
silicon
carbide barrier
silicon substrate
silicon carbide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3853351T
Other languages
English (en)
Other versions
DE3853351T2 (de
Inventor
Yuji Furumura
Fumitake Mieno
Takashi Eshita
Kikuo Itoh
Masahiko Doki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE3853351D1 publication Critical patent/DE3853351D1/de
Application granted granted Critical
Publication of DE3853351T2 publication Critical patent/DE3853351T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
DE3853351T 1987-12-17 1988-12-16 Siliciumcarbidsperre zwischen einem Siliciumsubstrat und einer Metallschicht. Expired - Fee Related DE3853351T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62317398A JP2546696B2 (ja) 1987-12-17 1987-12-17 シリコン炭化層構造

Publications (2)

Publication Number Publication Date
DE3853351D1 true DE3853351D1 (de) 1995-04-20
DE3853351T2 DE3853351T2 (de) 1995-07-27

Family

ID=18087801

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3853351T Expired - Fee Related DE3853351T2 (de) 1987-12-17 1988-12-16 Siliciumcarbidsperre zwischen einem Siliciumsubstrat und einer Metallschicht.

Country Status (5)

Country Link
US (1) US5103285A (de)
EP (1) EP0322161B1 (de)
JP (1) JP2546696B2 (de)
KR (1) KR920008033B1 (de)
DE (1) DE3853351T2 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5323343A (en) * 1989-10-26 1994-06-21 Mitsubishi Denki Kabushiki Kaisha DRAM device comprising a stacked type capacitor and a method of manufacturing thereof
JPH0496336A (ja) * 1990-08-11 1992-03-27 Nec Corp Ｍｏｓ型半導体装置
KR940006689B1 (ko) * 1991-10-21 1994-07-25 삼성전자 주식회사 반도체장치의 접촉창 형성방법
US5307305A (en) * 1991-12-04 1994-04-26 Rohm Co., Ltd. Semiconductor device having field effect transistor using ferroelectric film as gate insulation film
US5397717A (en) * 1993-07-12 1995-03-14 Motorola, Inc. Method of fabricating a silicon carbide vertical MOSFET
JP3045946B2 (ja) * 1994-05-09 2000-05-29 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体デバイスの製造方法
US5818071A (en) * 1995-02-02 1998-10-06 Dow Corning Corporation Silicon carbide metal diffusion barrier layer
US5759623A (en) * 1995-09-14 1998-06-02 Universite De Montreal Method for producing a high adhesion thin film of diamond on a Fe-based substrate
JP3305197B2 (ja) * 1995-09-14 2002-07-22 株式会社東芝 半導体装置
JPH11163329A (ja) * 1997-11-27 1999-06-18 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2000058783A (ja) * 1998-08-06 2000-02-25 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6124627A (en) * 1998-12-03 2000-09-26 Texas Instruments Incorporated Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region
US6531751B1 (en) * 1998-12-03 2003-03-11 Agere Systems Inc. Semiconductor device with increased gate insulator lifetime
JP2001035943A (ja) * 1999-07-23 2001-02-09 Mitsubishi Electric Corp 半導体装置および製造方法
US6492267B1 (en) * 2000-02-11 2002-12-10 Micron Technology, Inc. Low temperature nitride used as Cu barrier layer
US6417092B1 (en) 2000-04-05 2002-07-09 Novellus Systems, Inc. Low dielectric constant etch stop films
US6764958B1 (en) * 2000-07-28 2004-07-20 Applied Materials Inc. Method of depositing dielectric films
JP3650727B2 (ja) * 2000-08-10 2005-05-25 Ｈｏｙａ株式会社 炭化珪素製造方法
US6537733B2 (en) 2001-02-23 2003-03-25 Applied Materials, Inc. Method of depositing low dielectric constant silicon carbide layers
KR100847926B1 (ko) * 2001-07-02 2008-07-22 다우 코닝 코포레이션 다공성 물질상의 ＳｉＣ:Ｈ 침착에 의해 개선된 금속 장벽거동
KR20030020072A (ko) * 2001-09-01 2003-03-08 주성엔지니어링(주) 유니폴라 정전척
US6656837B2 (en) * 2001-10-11 2003-12-02 Applied Materials, Inc. Method of eliminating photoresist poisoning in damascene applications
US6528423B1 (en) * 2001-10-26 2003-03-04 Lsi Logic Corporation Process for forming composite of barrier layers of dielectric material to inhibit migration of copper from copper metal interconnect of integrated circuit structure into adjacent layer of low k dielectric material
GB0129567D0 (en) 2001-12-11 2002-01-30 Trikon Technologies Ltd Diffusion barrier
EP1842940A1 (de) * 2006-04-06 2007-10-10 Interuniversitair Microelektronica Centrum ( Imec) Verfahren zur Herstellung eines III-Nitridmaterials auf einem Siliziumsubstrat
WO2009058580A1 (en) * 2007-10-31 2009-05-07 Bae Systems Information And Electronic Systems Integration Inc. High-injection heterojunction bipolar transistor
WO2010147839A2 (en) * 2009-06-18 2010-12-23 Analog Devices, Inc. Silicon-rich nitride etch stop layer for vapor hf etching in mems device fabrication
US9099578B2 (en) 2012-06-04 2015-08-04 Nusola, Inc. Structure for creating ohmic contact in semiconductor devices and methods for manufacture

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3794516A (en) * 1970-12-15 1974-02-26 W Engeler Method for making high temperature low ohmic contact to silicon
JPS6271271A (ja) * 1985-09-24 1987-04-01 Sharp Corp 炭化珪素半導体の電極構造
JP2615390B2 (ja) * 1985-10-07 1997-05-28 工業技術院長 炭化シリコン電界効果トランジスタの製造方法
US4722913A (en) * 1986-10-17 1988-02-02 Thomson Components-Mostek Corporation Doped semiconductor vias to contacts
JPS63136568A (ja) * 1986-11-27 1988-06-08 Fujitsu Ltd 半導体装置
JP2534525B2 (ja) * 1987-12-19 1996-09-18 富士通株式会社 β−炭化シリコン層の製造方法

Also Published As

Publication number Publication date
EP0322161B1 (de) 1995-03-15
KR890011040A (ko) 1989-08-12
JPH01160055A (ja) 1989-06-22
EP0322161A3 (en) 1990-01-17
EP0322161A2 (de) 1989-06-28
DE3853351T2 (de) 1995-07-27
KR920008033B1 (ko) 1992-09-21
US5103285A (en) 1992-04-07
JP2546696B2 (ja) 1996-10-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee