DE3837080C2 - - Google Patents
Info
- Publication number
- DE3837080C2 DE3837080C2 DE3837080A DE3837080A DE3837080C2 DE 3837080 C2 DE3837080 C2 DE 3837080C2 DE 3837080 A DE3837080 A DE 3837080A DE 3837080 A DE3837080 A DE 3837080A DE 3837080 C2 DE3837080 C2 DE 3837080C2
- Authority
- DE
- Germany
- Prior art keywords
- field effect
- effect device
- signal
- level
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/316—Testing of analog circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Measurement Of Current Or Voltage (AREA)
- Tests Of Electronic Circuits (AREA)
- Electronic Switches (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62277969A JPH01119773A (ja) | 1987-11-02 | 1987-11-02 | インバータ回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE3837080A1 DE3837080A1 (de) | 1989-05-11 |
| DE3837080C2 true DE3837080C2 (OSRAM) | 1989-11-09 |
Family
ID=17590790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE3837080A Granted DE3837080A1 (de) | 1987-11-02 | 1988-10-31 | Inverterschaltung |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4916385A (OSRAM) |
| JP (1) | JPH01119773A (OSRAM) |
| DE (1) | DE3837080A1 (OSRAM) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002026134A (ja) * | 2000-07-12 | 2002-01-25 | Seiko Epson Corp | 半導体集積回路の製造方法及びこの方法により製造した半導体集積回路 |
| KR100602215B1 (ko) * | 2005-02-28 | 2006-07-19 | 삼성전자주식회사 | 임펄스 발생기 |
| JP6403524B2 (ja) * | 2014-09-29 | 2018-10-10 | キヤノン株式会社 | 電源装置および制御方法 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6035756B2 (ja) * | 1977-12-27 | 1985-08-16 | 日本電気株式会社 | 論理回路 |
| JPS6041364B2 (ja) * | 1980-08-29 | 1985-09-17 | 富士通株式会社 | 出力バッファ回路 |
| US4421994A (en) * | 1981-11-02 | 1983-12-20 | Ibm Corporation | High speed line driver with ground output capability |
| US4477741A (en) * | 1982-03-29 | 1984-10-16 | International Business Machines Corporation | Dynamic output impedance for 3-state drivers |
| US4760279A (en) * | 1986-07-02 | 1988-07-26 | Kabushiki Kaisha Toshiba | Noise cancelling circuit |
| JPS63115419A (ja) * | 1986-10-31 | 1988-05-20 | Fujitsu Ltd | Ttl回路 |
| US4777389A (en) * | 1987-08-13 | 1988-10-11 | Advanced Micro Devices, Inc. | Output buffer circuits for reducing ground bounce noise |
| US4782252A (en) * | 1987-12-08 | 1988-11-01 | Advanced Micro Devices, Inc. | Output current control circuit for reducing ground bounce noise |
| US4820942A (en) * | 1988-01-27 | 1989-04-11 | Advanced Micro Devices, Inc. | High-speed, high-drive output buffer circuits with reduced ground bounce |
-
1987
- 1987-11-02 JP JP62277969A patent/JPH01119773A/ja active Pending
-
1988
- 1988-10-25 US US07/262,302 patent/US4916385A/en not_active Expired - Lifetime
- 1988-10-31 DE DE3837080A patent/DE3837080A1/de active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01119773A (ja) | 1989-05-11 |
| US4916385A (en) | 1990-04-10 |
| DE3837080A1 (de) | 1989-05-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OP8 | Request for examination as to paragraph 44 patent law | ||
| D2 | Grant after examination | ||
| 8364 | No opposition during term of opposition | ||
| 8320 | Willingness to grant licences declared (paragraph 23) | ||
| 8328 | Change in the person/name/address of the agent |
Representative=s name: PRUFER & PARTNER GBR, 81545 MUENCHEN |
|
| 8339 | Ceased/non-payment of the annual fee |