DE3789987D1 - Halbleiterspeichervorrichtung mit einem Testmodus und einem Standardmodusbetrieb. - Google Patents

Halbleiterspeichervorrichtung mit einem Testmodus und einem Standardmodusbetrieb.

Info

Publication number
DE3789987D1
DE3789987D1 DE3789987T DE3789987T DE3789987D1 DE 3789987 D1 DE3789987 D1 DE 3789987D1 DE 3789987 T DE3789987 T DE 3789987T DE 3789987 T DE3789987 T DE 3789987T DE 3789987 D1 DE3789987 D1 DE 3789987D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
test mode
standard
mode operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3789987T
Other languages
English (en)
Other versions
DE3789987T2 (de
Inventor
Takeshi C O Nec Corpo Mizukami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE3789987D1 publication Critical patent/DE3789987D1/de
Application granted granted Critical
Publication of DE3789987T2 publication Critical patent/DE3789987T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/88—Monitoring involving counting
DE3789987T 1986-03-24 1987-03-24 Halbleiterspeichervorrichtung mit einem Testmodus und einem Standardmodusbetrieb. Expired - Lifetime DE3789987T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6650986 1986-03-24

Publications (2)

Publication Number Publication Date
DE3789987D1 true DE3789987D1 (de) 1994-07-14
DE3789987T2 DE3789987T2 (de) 1994-12-15

Family

ID=13317874

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3789987T Expired - Lifetime DE3789987T2 (de) 1986-03-24 1987-03-24 Halbleiterspeichervorrichtung mit einem Testmodus und einem Standardmodusbetrieb.

Country Status (4)

Country Link
US (1) US4807196A (de)
EP (1) EP0239916B1 (de)
JP (1) JPH0799618B2 (de)
DE (1) DE3789987T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0463210B1 (de) * 1990-06-27 1995-05-31 International Business Machines Corporation Verfahren und Vorrichtung zur Prüfung des Inhalts und der Adresse einer Speicheranordnung
US5216635A (en) * 1991-07-24 1993-06-01 Ncr Corporation System and method for requesting access to a computer memory for refreshing
JPH05274860A (ja) * 1992-03-26 1993-10-22 Nec Corp 半導体メモリ
KR950009390B1 (ko) * 1992-04-22 1995-08-21 삼성전자주식회사 반도체 메모리장치의 리프레시 어드레스 테스트회로
JP2870312B2 (ja) * 1992-07-28 1999-03-17 日本電気株式会社 半導体メモリ回路の調整方法
US5519876A (en) * 1993-12-23 1996-05-21 Unisys Corporation Processor communications bus having address lines selecting different storage locations based on selected control lines
JP3260583B2 (ja) * 1995-04-04 2002-02-25 株式会社東芝 ダイナミック型半導体メモリおよびそのテスト方法
US5793776A (en) * 1996-10-18 1998-08-11 Samsung Electronics Co., Ltd. Structure and method for SDRAM dynamic self refresh entry and exit using JTAG
JP3967559B2 (ja) * 2001-04-06 2007-08-29 富士通株式会社 制御回路及び半導体記憶装置
JP4408193B2 (ja) * 2002-08-08 2010-02-03 富士通マイクロエレクトロニクス株式会社 半導体記憶装置及び半導体記憶装置の試験方法
US7042785B2 (en) 2003-12-19 2006-05-09 Infineon Technologies, Ag Method and apparatus for controlling refresh cycles of a plural cycle refresh scheme in a dynamic memory
KR101197273B1 (ko) 2011-01-27 2012-11-05 에스케이하이닉스 주식회사 리프레쉬회로
US10957376B1 (en) * 2019-12-18 2021-03-23 Winbond Electronics Corp. Refresh testing circuit and method

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0019150B1 (de) * 1979-05-15 1984-07-18 Mostek Corporation Verfahren und Schaltung zum Prüfen der Arbeitsweise eines internen Regenerierungszählers in einem Speicher mit wahlfreiem Zugriff
US4453237A (en) * 1980-10-01 1984-06-05 Intel Corporation Multiple bit output dynamic random-access memory
US4406013A (en) * 1980-10-01 1983-09-20 Intel Corporation Multiple bit output dynamic random-access memory
US4672583A (en) * 1983-06-15 1987-06-09 Nec Corporation Dynamic random access memory device provided with test circuit for internal refresh circuit
JPS6020396A (ja) * 1983-07-15 1985-02-01 Hitachi Ltd 信号入力回路
JPS6148200A (ja) * 1984-08-14 1986-03-08 Fujitsu Ltd 半導体記憶装置
JPS6166295A (ja) * 1984-09-10 1986-04-05 Nec Corp 半導体メモリ
US4691303A (en) * 1985-10-31 1987-09-01 Sperry Corporation Refresh system for multi-bank semiconductor memory

Also Published As

Publication number Publication date
JPS6313198A (ja) 1988-01-20
JPH0799618B2 (ja) 1995-10-25
EP0239916A2 (de) 1987-10-07
EP0239916A3 (en) 1989-06-14
EP0239916B1 (de) 1994-06-08
US4807196A (en) 1989-02-21
DE3789987T2 (de) 1994-12-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKIO/TOKYO, JP