DE3788981T2 - Verfahren zur Herstellung von integrierten Schaltungen unter Verwendung einer mehrschichtigen Photolackstruktur. - Google Patents

Verfahren zur Herstellung von integrierten Schaltungen unter Verwendung einer mehrschichtigen Photolackstruktur.

Info

Publication number
DE3788981T2
DE3788981T2 DE19873788981 DE3788981T DE3788981T2 DE 3788981 T2 DE3788981 T2 DE 3788981T2 DE 19873788981 DE19873788981 DE 19873788981 DE 3788981 T DE3788981 T DE 3788981T DE 3788981 T2 DE3788981 T2 DE 3788981T2
Authority
DE
Germany
Prior art keywords
integrated circuits
manufacturing integrated
photoresist structure
multilayer photoresist
multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19873788981
Other languages
English (en)
Other versions
DE3788981D1 (de
Inventor
Avinoam Kornblit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Application granted granted Critical
Publication of DE3788981D1 publication Critical patent/DE3788981D1/de
Publication of DE3788981T2 publication Critical patent/DE3788981T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
DE19873788981 1986-06-26 1987-06-17 Verfahren zur Herstellung von integrierten Schaltungen unter Verwendung einer mehrschichtigen Photolackstruktur. Expired - Fee Related DE3788981T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US87860686A 1986-06-26 1986-06-26

Publications (2)

Publication Number Publication Date
DE3788981D1 DE3788981D1 (de) 1994-03-17
DE3788981T2 true DE3788981T2 (de) 1994-05-19

Family

ID=25372380

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19873788981 Expired - Fee Related DE3788981T2 (de) 1986-06-26 1987-06-17 Verfahren zur Herstellung von integrierten Schaltungen unter Verwendung einer mehrschichtigen Photolackstruktur.

Country Status (5)

Country Link
EP (1) EP0251566B1 (de)
JP (1) JP2768462B2 (de)
CA (1) CA1289682C (de)
DE (1) DE3788981T2 (de)
ES (1) ES2048158T3 (de)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4244799A (en) * 1978-09-11 1981-01-13 Bell Telephone Laboratories, Incorporated Fabrication of integrated circuits utilizing thick high-resolution patterns
NL8004008A (nl) * 1980-07-11 1982-02-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleider- inrichting.
JPS59163826A (ja) * 1983-03-08 1984-09-14 Toshiba Corp ドライエツチング方法
JPS59169137A (ja) * 1983-03-16 1984-09-25 Fujitsu Ltd 有機膜のパタ−ン形成方法

Also Published As

Publication number Publication date
CA1289682C (en) 1991-09-24
DE3788981D1 (de) 1994-03-17
JP2768462B2 (ja) 1998-06-25
EP0251566A1 (de) 1988-01-07
JPS6333823A (ja) 1988-02-13
EP0251566B1 (de) 1994-02-02
ES2048158T3 (es) 1994-03-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN

8339 Ceased/non-payment of the annual fee