DE3786768D1 - Halbleitergeraet mit programmierbaren nur-lesespeicherzellen fuer spezifischen modus. - Google Patents
Halbleitergeraet mit programmierbaren nur-lesespeicherzellen fuer spezifischen modus.Info
- Publication number
- DE3786768D1 DE3786768D1 DE8787310864T DE3786768T DE3786768D1 DE 3786768 D1 DE3786768 D1 DE 3786768D1 DE 8787310864 T DE8787310864 T DE 8787310864T DE 3786768 T DE3786768 T DE 3786768T DE 3786768 D1 DE3786768 D1 DE 3786768D1
- Authority
- DE
- Germany
- Prior art keywords
- programmable
- read
- semiconductor device
- specific mode
- storage cells
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7814—Specially adapted for real time processing, e.g. comprising hardware timers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61302811A JPH0752217B2 (ja) | 1986-12-20 | 1986-12-20 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3786768D1 true DE3786768D1 (de) | 1993-09-02 |
DE3786768T2 DE3786768T2 (de) | 1993-11-18 |
Family
ID=17913385
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE87310864T Expired - Fee Related DE3786768T2 (de) | 1986-12-20 | 1987-12-10 | Halbleitergerät mit programmierbaren Nur-Lesespeicherzellen für spezifischen Modus. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4965768A (de) |
EP (1) | EP0272848B1 (de) |
JP (1) | JPH0752217B2 (de) |
KR (1) | KR910005033B1 (de) |
DE (1) | DE3786768T2 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0670776B2 (ja) * | 1990-02-23 | 1994-09-07 | 株式会社東芝 | 半導体集積回路 |
US5072137A (en) * | 1990-08-17 | 1991-12-10 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with a clocked access code for test mode entry |
US5072138A (en) * | 1990-08-17 | 1991-12-10 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with sequential clocked access codes for test mode entry |
US5155704A (en) * | 1990-10-16 | 1992-10-13 | Micron Technology, Inc. | Memory integrated circuit test mode switching |
JP3282188B2 (ja) * | 1991-06-27 | 2002-05-13 | 日本電気株式会社 | 半導体メモリ装置 |
US5497475A (en) * | 1993-02-05 | 1996-03-05 | National Semiconductor Corporation | Configurable integrated circuit having true and shadow EPROM registers |
JPH06243677A (ja) * | 1993-02-19 | 1994-09-02 | Hitachi Ltd | 半導体記憶装置とメモリ装置及びその品種設定方法 |
JPH06274656A (ja) * | 1993-03-20 | 1994-09-30 | Hitachi Ltd | マイクロコンピュータ |
DE19819265C1 (de) * | 1998-04-30 | 1999-08-19 | Micronas Intermetall Gmbh | Verfahren zum Parametrieren einer integrierten Schaltungsanordnung und integrierte Schaltungsanordnung hierfür |
JP2002176344A (ja) * | 2000-07-12 | 2002-06-21 | Texas Instruments Inc | ヒューズ回路 |
CN110927562B (zh) * | 2019-12-19 | 2022-08-05 | 西安紫光国芯半导体有限公司 | 一种兼容老化测试的方法及其芯片 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4301535A (en) * | 1979-07-02 | 1981-11-17 | Mostek Corporation | Programmable read only memory integrated circuit with bit-check and deprogramming modes and methods for programming and testing said circuit |
US4380805A (en) * | 1980-09-08 | 1983-04-19 | Mostek Corporation | Tape burn-in circuit |
GB2094086B (en) * | 1981-03-03 | 1985-08-14 | Tokyo Shibaura Electric Co | Non-volatile semiconductor memory system |
JPS5885995A (ja) * | 1981-11-18 | 1983-05-23 | Nec Corp | 記憶装置 |
DE3232215A1 (de) * | 1982-08-30 | 1984-03-01 | Siemens AG, 1000 Berlin und 8000 München | Monolithisch integrierte digitale halbleiterschaltung |
JPS59121699A (ja) * | 1982-12-28 | 1984-07-13 | Toshiba Corp | 冗長性回路変更装置 |
US4658380A (en) * | 1986-02-28 | 1987-04-14 | Ncr Corporation | CMOS memory margining control circuit for a nonvolatile memory |
-
1986
- 1986-12-20 JP JP61302811A patent/JPH0752217B2/ja not_active Expired - Fee Related
-
1987
- 1987-12-08 US US07/130,691 patent/US4965768A/en not_active Expired - Lifetime
- 1987-12-10 DE DE87310864T patent/DE3786768T2/de not_active Expired - Fee Related
- 1987-12-10 EP EP87310864A patent/EP0272848B1/de not_active Expired - Lifetime
- 1987-12-17 KR KR1019870014436A patent/KR910005033B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0272848B1 (de) | 1993-07-28 |
DE3786768T2 (de) | 1993-11-18 |
EP0272848A2 (de) | 1988-06-29 |
KR910005033B1 (ko) | 1991-07-22 |
KR880008341A (ko) | 1988-08-30 |
EP0272848A3 (en) | 1990-04-18 |
JPS63157077A (ja) | 1988-06-30 |
US4965768A (en) | 1990-10-23 |
JPH0752217B2 (ja) | 1995-06-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |