DE3780795D1 - Verfahren zur herstellung einer halbleiteranordnung vom typ "halbleiter auf isolator". - Google Patents

Verfahren zur herstellung einer halbleiteranordnung vom typ "halbleiter auf isolator".

Info

Publication number
DE3780795D1
DE3780795D1 DE8787202644T DE3780795T DE3780795D1 DE 3780795 D1 DE3780795 D1 DE 3780795D1 DE 8787202644 T DE8787202644 T DE 8787202644T DE 3780795 T DE3780795 T DE 3780795T DE 3780795 D1 DE3780795 D1 DE 3780795D1
Authority
DE
Germany
Prior art keywords
semiconductor
isolator
producing
type
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787202644T
Other languages
English (en)
Other versions
DE3780795T2 (de
Inventor
Elizabeth Maria Leon Alexander
Jan Haisma
Theodorus Martinus Michielsen
Der Velden Johannes Wilhel Van
Johannes Franciscus Verhoeven
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE3780795D1 publication Critical patent/DE3780795D1/de
Application granted granted Critical
Publication of DE3780795T2 publication Critical patent/DE3780795T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/164—Three dimensional processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE8787202644T 1987-01-09 1987-12-29 Verfahren zur herstellung einer halbleiteranordnung vom typ "halbleiter auf isolator". Expired - Fee Related DE3780795T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8700033A NL8700033A (nl) 1987-01-09 1987-01-09 Werkwijze voor het vervaardigen van een halfgeleiderinrichting van het type halfgeleider op isolator.

Publications (2)

Publication Number Publication Date
DE3780795D1 true DE3780795D1 (de) 1992-09-03
DE3780795T2 DE3780795T2 (de) 1993-03-04

Family

ID=19849387

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787202644T Expired - Fee Related DE3780795T2 (de) 1987-01-09 1987-12-29 Verfahren zur herstellung einer halbleiteranordnung vom typ "halbleiter auf isolator".

Country Status (6)

Country Link
US (1) US4971925A (de)
EP (1) EP0274801B1 (de)
JP (1) JP2847671B2 (de)
KR (1) KR970000648B1 (de)
DE (1) DE3780795T2 (de)
NL (1) NL8700033A (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8800953A (nl) * 1988-04-13 1989-11-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderlichaam.
JPH02146732A (ja) * 1988-07-28 1990-06-05 Fujitsu Ltd 研摩液及び研摩方法
EP0363100A3 (de) * 1988-10-02 1990-05-23 Canon Kabushiki Kaisha Selektives Polierverfahren
JP2577090B2 (ja) * 1989-08-07 1997-01-29 キヤノン株式会社 結晶半導体膜の形成方法
JP2541884B2 (ja) * 1991-08-31 1996-10-09 信越半導体株式会社 誘電体分離基板の製造方法
JP2833305B2 (ja) * 1991-12-05 1998-12-09 富士通株式会社 半導体基板の製造方法
US5334281A (en) * 1992-04-30 1994-08-02 International Business Machines Corporation Method of forming thin silicon mesas having uniform thickness
US5234846A (en) * 1992-04-30 1993-08-10 International Business Machines Corporation Method of making bipolar transistor with reduced topography
US5258318A (en) * 1992-05-15 1993-11-02 International Business Machines Corporation Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon
US5302842A (en) * 1992-07-20 1994-04-12 Bell Communications Research, Inc. Field-effect transistor formed over gate electrode
US5262346A (en) * 1992-12-16 1993-11-16 International Business Machines Corporation Nitride polish stop for forming SOI wafers
US5318663A (en) * 1992-12-23 1994-06-07 International Business Machines Corporation Method for thinning SOI films having improved thickness uniformity
WO2004077537A1 (ja) * 1993-01-18 2004-09-10 Shinsuke Sakai 半導体基板の製造方法
US5376580A (en) * 1993-03-19 1994-12-27 Hewlett-Packard Company Wafer bonding of light emitting diode layers
JP3301170B2 (ja) * 1993-08-09 2002-07-15 ソニー株式会社 半導体装置の製法
JP3033655B2 (ja) * 1993-09-28 2000-04-17 日本電気株式会社 半導体装置及び半導体装置の製造方法
US5358887A (en) * 1993-11-26 1994-10-25 United Microelectronics Corporation Ulsi mask ROM structure and method of manufacture
US5449638A (en) * 1994-06-06 1995-09-12 United Microelectronics Corporation Process on thickness control for silicon-on-insulator technology
US5496764A (en) * 1994-07-05 1996-03-05 Motorola, Inc. Process for forming a semiconductor region adjacent to an insulating layer
US6484585B1 (en) 1995-02-28 2002-11-26 Rosemount Inc. Pressure sensor for a pressure transmitter
US5637802A (en) * 1995-02-28 1997-06-10 Rosemount Inc. Capacitive pressure sensor for a pressure transmitted where electric field emanates substantially from back sides of plates
US5583072A (en) * 1995-06-30 1996-12-10 Siemens Components, Inc. Method of manufacturing a monolithic linear optocoupler
US5708264A (en) * 1995-11-07 1998-01-13 Eastman Kodak Company Planar color filter array for CCDs from dyed and mordant layers
US5677202A (en) * 1995-11-20 1997-10-14 Eastman Kodak Company Method for making planar color filter array for image sensors with embedded color filter arrays
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6500694B1 (en) * 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6508129B1 (en) 2000-01-06 2003-01-21 Rosemount Inc. Pressure sensor capsule with improved isolation
US6520020B1 (en) 2000-01-06 2003-02-18 Rosemount Inc. Method and apparatus for a direct bonded isolated pressure sensor
US6505516B1 (en) 2000-01-06 2003-01-14 Rosemount Inc. Capacitive pressure sensing with moving dielectric
JP3620795B2 (ja) 2000-01-06 2005-02-16 ローズマウント インコーポレイテッド 超小型電気機械システム用電気的相互接続部の結晶粒成長
US6561038B2 (en) 2000-01-06 2003-05-13 Rosemount Inc. Sensor with fluid isolation barrier
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3508980A (en) * 1967-07-26 1970-04-28 Motorola Inc Method of fabricating an integrated circuit structure with dielectric isolation
US3689357A (en) * 1970-12-10 1972-09-05 Gen Motors Corp Glass-polysilicon dielectric isolation
US3938176A (en) * 1973-09-24 1976-02-10 Texas Instruments Incorporated Process for fabricating dielectrically isolated semiconductor components of an integrated circuit
JPS5099684A (de) * 1973-12-29 1975-08-07
JPS5539902B2 (de) * 1973-12-29 1980-10-14
US3911562A (en) * 1974-01-14 1975-10-14 Signetics Corp Method of chemical polishing of planar silicon structures having filled grooves therein
JPS57128942A (en) * 1981-02-02 1982-08-10 Jido Keisoku Gijutsu Kenkiyuukumiai Manufacture of insulation isolating substrate
US4501060A (en) * 1983-01-24 1985-02-26 At&T Bell Laboratories Dielectrically isolated semiconductor devices
JPS59188138A (ja) * 1983-04-08 1984-10-25 Nec Corp 半導体装置の製造方法
JPS6039835A (ja) * 1983-08-12 1985-03-01 Hitachi Ltd 基板表面の平坦化方法
NL8501773A (nl) * 1985-06-20 1987-01-16 Philips Nv Werkwijze voor het vervaardigen van halfgeleiderinrichtingen.
JPH0783050B2 (ja) * 1985-06-21 1995-09-06 株式会社東芝 半導体素子の製造方法
US4671851A (en) * 1985-10-28 1987-06-09 International Business Machines Corporation Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique
JPS6356936A (ja) * 1986-08-27 1988-03-11 Nec Corp 半導体装置の製造方法
US4735679A (en) * 1987-03-30 1988-04-05 International Business Machines Corporation Method of improving silicon-on-insulator uniformity
US4851078A (en) * 1987-06-29 1989-07-25 Harris Corporation Dielectric isolation process using double wafer bonding
US4784970A (en) * 1987-11-18 1988-11-15 Grumman Aerospace Corporation Process for making a double wafer moated signal processor
US4794092A (en) * 1987-11-18 1988-12-27 Grumman Aerospace Corporation Single wafer moated process

Also Published As

Publication number Publication date
EP0274801A2 (de) 1988-07-20
EP0274801A3 (en) 1988-08-17
KR970000648B1 (ko) 1997-01-16
JP2847671B2 (ja) 1999-01-20
KR880009430A (ko) 1988-09-15
NL8700033A (nl) 1988-08-01
DE3780795T2 (de) 1993-03-04
JPS647548A (en) 1989-01-11
US4971925A (en) 1990-11-20
EP0274801B1 (de) 1992-07-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee