DE3638632C2 - - Google Patents

Info

Publication number
DE3638632C2
DE3638632C2 DE3638632A DE3638632A DE3638632C2 DE 3638632 C2 DE3638632 C2 DE 3638632C2 DE 3638632 A DE3638632 A DE 3638632A DE 3638632 A DE3638632 A DE 3638632A DE 3638632 C2 DE3638632 C2 DE 3638632C2
Authority
DE
Germany
Prior art keywords
cells
parity
circuits
cell
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3638632A
Other languages
German (de)
English (en)
Other versions
DE3638632A1 (de
Inventor
Junzo Atsugi Kanagawa Jp Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP60253396A external-priority patent/JPS62112299A/ja
Priority claimed from JP61092517A external-priority patent/JPS62248200A/ja
Priority claimed from JP61092516A external-priority patent/JPS62248199A/ja
Priority claimed from JP61092515A external-priority patent/JPS62248198A/ja
Priority claimed from JP61161715A external-priority patent/JPS6318598A/ja
Priority claimed from JP61161716A external-priority patent/JPS6318599A/ja
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Publication of DE3638632A1 publication Critical patent/DE3638632A1/de
Application granted granted Critical
Publication of DE3638632C2 publication Critical patent/DE3638632C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE19863638632 1985-11-12 1986-11-11 Halbleiterspeicher Granted DE3638632A1 (de)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP60253396A JPS62112299A (ja) 1985-11-12 1985-11-12 自己訂正半導体メモリ
JP61092517A JPS62248200A (ja) 1986-04-21 1986-04-21 自己訂正半導体記憶装置
JP61092516A JPS62248199A (ja) 1986-04-21 1986-04-21 自己訂正半導体メモリ
JP61092515A JPS62248198A (ja) 1986-04-21 1986-04-21 半導体記憶装置
JP61161715A JPS6318598A (ja) 1986-07-09 1986-07-09 自己訂正半導体メモリ
JP61161716A JPS6318599A (ja) 1986-07-09 1986-07-09 半導体メモリ

Publications (2)

Publication Number Publication Date
DE3638632A1 DE3638632A1 (de) 1987-05-14
DE3638632C2 true DE3638632C2 (en, 2012) 1989-03-02

Family

ID=27551873

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19863638632 Granted DE3638632A1 (de) 1985-11-12 1986-11-11 Halbleiterspeicher

Country Status (3)

Country Link
US (1) US4747080A (en, 2012)
KR (1) KR900009124B1 (en, 2012)
DE (1) DE3638632A1 (en, 2012)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0814985B2 (ja) * 1989-06-06 1996-02-14 富士通株式会社 半導体記憶装置
JPH07113904B2 (ja) * 1990-04-11 1995-12-06 株式会社東芝 メモリ・アクセス装置
US5164944A (en) * 1990-06-08 1992-11-17 Unisys Corporation Method and apparatus for effecting multiple error correction in a computer memory
US6125466A (en) * 1992-01-10 2000-09-26 Cabletron Systems, Inc. DRAM parity protection scheme
US5383146A (en) * 1992-06-08 1995-01-17 Music Semiconductors, Inc. Memory with CAM and RAM partitions
US5513192A (en) * 1992-08-28 1996-04-30 Sun Microsystems, Inc. Fault tolerant disk drive system with error detection and correction
US6199140B1 (en) * 1997-10-30 2001-03-06 Netlogic Microsystems, Inc. Multiport content addressable memory device and timing signals
US6148364A (en) * 1997-12-30 2000-11-14 Netlogic Microsystems, Inc. Method and apparatus for cascading content addressable memory devices
US6240485B1 (en) 1998-05-11 2001-05-29 Netlogic Microsystems, Inc. Method and apparatus for implementing a learn instruction in a depth cascaded content addressable memory system
US6219748B1 (en) 1998-05-11 2001-04-17 Netlogic Microsystems, Inc. Method and apparatus for implementing a learn instruction in a content addressable memory device
US5966339A (en) * 1998-06-02 1999-10-12 International Business Machines Corporation Programmable/reprogrammable fuse
US6381673B1 (en) 1998-07-06 2002-04-30 Netlogic Microsystems, Inc. Method and apparatus for performing a read next highest priority match instruction in a content addressable memory device
US6574702B2 (en) 1999-02-23 2003-06-03 Netlogic Microsystems, Inc. Method and apparatus for determining an exact match in a content addressable memory device
US6499081B1 (en) 1999-02-23 2002-12-24 Netlogic Microsystems, Inc. Method and apparatus for determining a longest prefix match in a segmented content addressable memory device
US6539455B1 (en) 1999-02-23 2003-03-25 Netlogic Microsystems, Inc. Method and apparatus for determining an exact match in a ternary content addressable memory device
US6892272B1 (en) 1999-02-23 2005-05-10 Netlogic Microsystems, Inc. Method and apparatus for determining a longest prefix match in a content addressable memory device
US6460112B1 (en) 1999-02-23 2002-10-01 Netlogic Microsystems, Llc Method and apparatus for determining a longest prefix match in a content addressable memory device
US6137707A (en) * 1999-03-26 2000-10-24 Netlogic Microsystems Method and apparatus for simultaneously performing a plurality of compare operations in content addressable memory device
US7110407B1 (en) 1999-09-23 2006-09-19 Netlogic Microsystems, Inc. Method and apparatus for performing priority encoding in a segmented classification system using enable signals
US6934795B2 (en) * 1999-09-23 2005-08-23 Netlogic Microsystems, Inc. Content addressable memory with programmable word width and programmable priority
US7487200B1 (en) 1999-09-23 2009-02-03 Netlogic Microsystems, Inc. Method and apparatus for performing priority encoding in a segmented classification system
US6944709B2 (en) * 1999-09-23 2005-09-13 Netlogic Microsystems, Inc. Content addressable memory with block-programmable mask write mode, word width and priority
US7272027B2 (en) * 1999-09-23 2007-09-18 Netlogic Microsystems, Inc. Priority circuit for content addressable memory
US7143231B1 (en) 1999-09-23 2006-11-28 Netlogic Microsystems, Inc. Method and apparatus for performing packet classification for policy-based packet routing
US6567340B1 (en) 1999-09-23 2003-05-20 Netlogic Microsystems, Inc. Memory storage cell based array of counters
US6532538B1 (en) * 2000-02-17 2003-03-11 International Business Machines Corporation Method and system for supporting multiple operating systems on the same disk running on different computers at the same time
US6700827B2 (en) 2001-02-08 2004-03-02 Integrated Device Technology, Inc. Cam circuit with error correction
US7283380B1 (en) 2001-08-03 2007-10-16 Netlogic Microsystems, Inc. Content addressable memory with selective error logging
US7043673B1 (en) 2001-08-03 2006-05-09 Netlogic Microsystems, Inc. Content addressable memory with priority-biased error detection sequencing
US6597595B1 (en) 2001-08-03 2003-07-22 Netlogic Microsystems, Inc. Content addressable memory with error detection signaling
US7002823B1 (en) 2001-08-03 2006-02-21 Netlogic Microsystems, Inc. Content addressable memory with simultaneous write and compare function
US7257763B1 (en) 2001-08-03 2007-08-14 Netlogic Microsystems, Inc. Content addressable memory with error signaling
US7237156B1 (en) 2001-08-03 2007-06-26 Netlogic Microsystems, Inc. Content addressable memory with error detection
US6914795B1 (en) 2001-08-03 2005-07-05 Netlogic Microsystems, Inc. Content addressable memory with selective error logging
US7301961B1 (en) 2001-12-27 2007-11-27 Cypress Semiconductor Corportion Method and apparatus for configuring signal lines according to idle codes
ITMI20020260A1 (it) * 2002-02-12 2003-08-12 Ausimont Spa Dispersioni acquose di fluoropolimeri
US6978343B1 (en) 2002-08-05 2005-12-20 Netlogic Microsystems, Inc. Error-correcting content addressable memory
US7010741B2 (en) 2002-10-29 2006-03-07 Mosaid Technologies Method and circuit for error correction in CAM cells
CA2447204C (en) * 2002-11-29 2010-03-23 Memory Management Services Ltd. Error correction scheme for memory
US7193876B1 (en) 2003-07-15 2007-03-20 Kee Park Content addressable memory (CAM) arrays having memory cells therein with different susceptibilities to soft errors
US6870749B1 (en) 2003-07-15 2005-03-22 Integrated Device Technology, Inc. Content addressable memory (CAM) devices with dual-function check bit cells that support column redundancy and check bit cells with reduced susceptibility to soft errors
US6987684B1 (en) 2003-07-15 2006-01-17 Integrated Device Technology, Inc. Content addressable memory (CAM) devices having multi-block error detection logic and entry selective error correction logic therein
US7304875B1 (en) 2003-12-17 2007-12-04 Integrated Device Technology. Inc. Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same
US7231582B2 (en) * 2003-12-19 2007-06-12 Stmicroelectronics, Inc. Method and system to encode and decode wide data words
US7321518B1 (en) * 2004-01-15 2008-01-22 Altera Corporation Apparatus and methods for providing redundancy in integrated circuits
US7304873B1 (en) 2005-01-25 2007-12-04 Netlogic Microsystems, Inc. Method for on-the-fly error correction in a content addressable memory (CAM) and device therefor
KR100694407B1 (ko) * 2005-04-21 2007-03-12 주식회사 하이닉스반도체 불량 셀 교정 회로를 포함하는 불휘발성 강유전체 메모리장치
US8055958B2 (en) * 2008-12-11 2011-11-08 Samsung Electronics Co., Ltd. Replacement data storage circuit storing address of defective memory cell
US8381052B2 (en) 2009-11-10 2013-02-19 International Business Machines Corporation Circuit and method for efficient memory repair
US8553441B1 (en) 2010-08-31 2013-10-08 Netlogic Microsystems, Inc. Ternary content addressable memory cell having two transistor pull-down stack
US8625320B1 (en) 2010-08-31 2014-01-07 Netlogic Microsystems, Inc. Quaternary content addressable memory cell having one transistor pull-down stack
US8582338B1 (en) 2010-08-31 2013-11-12 Netlogic Microsystems, Inc. Ternary content addressable memory cell having single transistor pull-down stack
US8462532B1 (en) 2010-08-31 2013-06-11 Netlogic Microsystems, Inc. Fast quaternary content addressable memory cell
KR101212759B1 (ko) * 2010-10-29 2012-12-14 에스케이하이닉스 주식회사 데이터 오류 검사 기능을 이용한 데이터 전송 방법, 데이터 오류 검사 기능을 이용한 반도체 메모리 및 메모리 시스템
US8990631B1 (en) 2011-03-03 2015-03-24 Netlogic Microsystems, Inc. Packet format for error reporting in a content addressable memory
US8773880B2 (en) 2011-06-23 2014-07-08 Netlogic Microsystems, Inc. Content addressable memory array having virtual ground nodes
US8837188B1 (en) 2011-06-23 2014-09-16 Netlogic Microsystems, Inc. Content addressable memory row having virtual ground and charge sharing
TWI497280B (zh) * 2013-07-08 2015-08-21 Phison Electronics Corp 資料保護方法、記憶體儲存裝置與記憶體控制器
WO2020251155A1 (en) 2019-06-13 2020-12-17 Samsung Electronics Co., Ltd. An automated system for healing faulty node in a network and method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6042560B2 (ja) * 1981-03-17 1985-09-24 日本電信電話株式会社 半導体記憶装置

Also Published As

Publication number Publication date
KR900009124B1 (ko) 1990-12-22
DE3638632A1 (de) 1987-05-14
KR870005391A (ko) 1987-06-08
US4747080A (en) 1988-05-24

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition