DE3587829D1 - Verfahren zur herstellung von untereinander selbstalignierten gräben unter verwendung einer maske. - Google Patents

Verfahren zur herstellung von untereinander selbstalignierten gräben unter verwendung einer maske.

Info

Publication number
DE3587829D1
DE3587829D1 DE3587829T DE3587829T DE3587829D1 DE 3587829 D1 DE3587829 D1 DE 3587829D1 DE 3587829 T DE3587829 T DE 3587829T DE 3587829 T DE3587829 T DE 3587829T DE 3587829 D1 DE3587829 D1 DE 3587829D1
Authority
DE
Germany
Prior art keywords
slots
mask
layer
different types
etch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3587829T
Other languages
English (en)
Other versions
DE3587829T2 (de
Inventor
Robert Bower
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE3587829D1 publication Critical patent/DE3587829D1/de
Application granted granted Critical
Publication of DE3587829T2 publication Critical patent/DE3587829T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Bipolar Transistors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Semiconductor Memories (AREA)
DE3587829T 1984-02-03 1985-02-01 Verfahren zur herstellung von untereinander selbstalignierten gräben unter verwendung einer maske. Expired - Fee Related DE3587829T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/576,658 US4579812A (en) 1984-02-03 1984-02-03 Process for forming slots of different types in self-aligned relationship using a latent image mask
PCT/US1985/000170 WO1985003580A1 (en) 1984-02-03 1985-02-01 Process for forming slots of different types in self-aligned relationship using a latent image mask

Publications (2)

Publication Number Publication Date
DE3587829D1 true DE3587829D1 (de) 1994-06-23
DE3587829T2 DE3587829T2 (de) 1994-11-10

Family

ID=24305393

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3587829T Expired - Fee Related DE3587829T2 (de) 1984-02-03 1985-02-01 Verfahren zur herstellung von untereinander selbstalignierten gräben unter verwendung einer maske.

Country Status (6)

Country Link
US (1) US4579812A (de)
EP (1) EP0172192B1 (de)
JP (1) JPH0714001B2 (de)
AT (1) ATE105973T1 (de)
DE (1) DE3587829T2 (de)
WO (1) WO1985003580A1 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6281727A (ja) * 1985-10-05 1987-04-15 Fujitsu Ltd 埋込型素子分離溝の形成方法
EP0286855A1 (de) * 1987-04-15 1988-10-19 BBC Brown Boveri AG Verfahren zum Aetzen von Vertiefungen in ein Siliziumsubstrat
US4895790A (en) * 1987-09-21 1990-01-23 Massachusetts Institute Of Technology High-efficiency, multilevel, diffractive optical elements
US5161059A (en) * 1987-09-21 1992-11-03 Massachusetts Institute Of Technology High-efficiency, multilevel, diffractive optical elements
US4863560A (en) * 1988-08-22 1989-09-05 Xerox Corp Fabrication of silicon structures by single side, multiple step etching process
US4997746A (en) * 1988-11-22 1991-03-05 Greco Nancy A Method of forming conductive lines and studs
US5143820A (en) * 1989-10-31 1992-09-01 International Business Machines Corporation Method for fabricating high circuit density, self-aligned metal linens to contact windows
EP0425787A3 (en) * 1989-10-31 1993-04-14 International Business Machines Corporation Method for fabricating high circuit density, self-aligned metal lines to contact windows
JP2652072B2 (ja) * 1990-02-26 1997-09-10 キヤノン株式会社 遮光層の形成方法
JP2519819B2 (ja) * 1990-05-09 1996-07-31 株式会社東芝 コンタクトホ―ルの形成方法
US5350618A (en) * 1991-03-01 1994-09-27 Teijin Seiki Co., Ltd. Magnetic medium comprising a substrate having pits and grooves of specific shapes and depths
US5470693A (en) * 1992-02-18 1995-11-28 International Business Machines Corporation Method of forming patterned polyimide films
US5308722A (en) * 1992-09-24 1994-05-03 Advanced Micro Devices Voting technique for the manufacture of defect-free printing phase shift lithography
JPH1056059A (ja) * 1996-08-09 1998-02-24 Nec Corp 半導体装置およびその製造方法
KR100226749B1 (ko) * 1997-04-24 1999-10-15 구본준 반도체 소자의 제조 방법
US6011297A (en) * 1997-07-18 2000-01-04 Advanced Micro Devices,Inc. Use of multiple slots surrounding base region of a bipolar junction transistor to increase cumulative breakdown voltage
US5859469A (en) * 1997-07-18 1999-01-12 Advanced Micro Devices, Inc. Use of tungsten filled slots as ground plane in integrated circuit structure
US5912501A (en) * 1997-07-18 1999-06-15 Advanced Micro Devices, Inc. Elimination of radius of curvature effects of p-n junction avalanche breakdown using slots
US5895253A (en) * 1997-08-22 1999-04-20 Micron Technology, Inc. Trench isolation for CMOS devices
US6175144B1 (en) * 1998-05-15 2001-01-16 Advanced Micro Devices, Inc. Advanced isolation structure for high density semiconductor devices
US6127276A (en) * 1998-06-02 2000-10-03 United Microelectronics Corp Method of formation for a via opening
AU7565400A (en) * 1999-09-17 2001-04-17 Telefonaktiebolaget Lm Ericsson (Publ) A self-aligned method for forming deep trenches in shallow trenches for isolation of semiconductor devices
US6818138B2 (en) * 2001-06-22 2004-11-16 Hewlett-Packard Development Company, L.P. Slotted substrate and slotting process
KR100474579B1 (ko) * 2002-08-09 2005-03-10 삼성전자주식회사 표면 분석 장치에 사용되는 표준 기판 제작 방법
US6794262B2 (en) * 2002-09-23 2004-09-21 Infineon Technologies Ag MIM capacitor structures and fabrication methods in dual-damascene structures
JP2004327910A (ja) * 2003-04-28 2004-11-18 Sharp Corp 半導体装置およびその製造方法
US9318378B2 (en) * 2004-08-21 2016-04-19 Globalfoundries Singapore Pte. Ltd. Slot designs in wide metal lines
US7105456B2 (en) * 2004-10-29 2006-09-12 Hewlett-Packard Development Company, Lp. Methods for controlling feature dimensions in crystalline substrates
KR101201903B1 (ko) * 2010-07-20 2012-11-16 매그나칩 반도체 유한회사 반도체소자의 소자분리 구조 및 그 형성방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3479237A (en) * 1966-04-08 1969-11-18 Bell Telephone Labor Inc Etch masks on semiconductor surfaces
US3542551A (en) * 1968-07-01 1970-11-24 Trw Semiconductors Inc Method of etching patterns into solid state devices
US4139442A (en) * 1977-09-13 1979-02-13 International Business Machines Corporation Reactive ion etching method for producing deep dielectric isolation in silicon
JPS5626450A (en) * 1979-08-13 1981-03-14 Hitachi Ltd Manufacture of semiconductor device
JPS5681968A (en) * 1979-12-07 1981-07-04 Toshiba Corp Manufacture of semiconductor device
JPS59124141A (ja) * 1982-12-28 1984-07-18 Toshiba Corp 半導体装置の製造方法
JPH0665225B2 (ja) * 1984-01-13 1994-08-22 株式会社東芝 半導体記憶装置の製造方法
US4495025A (en) * 1984-04-06 1985-01-22 Advanced Micro Devices, Inc. Process for forming grooves having different depths using a single masking step

Also Published As

Publication number Publication date
US4579812A (en) 1986-04-01
WO1985003580A1 (en) 1985-08-15
EP0172192A4 (de) 1989-08-30
JPS61501235A (ja) 1986-06-19
EP0172192A1 (de) 1986-02-26
EP0172192B1 (de) 1994-05-18
JPH0714001B2 (ja) 1995-02-15
DE3587829T2 (de) 1994-11-10
ATE105973T1 (de) 1994-06-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee