DE3486261T2 - Speichermatrix. - Google Patents

Speichermatrix.

Info

Publication number
DE3486261T2
DE3486261T2 DE84306928T DE3486261T DE3486261T2 DE 3486261 T2 DE3486261 T2 DE 3486261T2 DE 84306928 T DE84306928 T DE 84306928T DE 3486261 T DE3486261 T DE 3486261T DE 3486261 T2 DE3486261 T2 DE 3486261T2
Authority
DE
Germany
Prior art keywords
transistors
emitters
emitter
collector
row
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE84306928T
Other languages
German (de)
English (en)
Other versions
DE3486261D1 (de
Inventor
Barry A Hoberman
William E Moss
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vantis Corp
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE3486261D1 publication Critical patent/DE3486261D1/de
Publication of DE3486261T2 publication Critical patent/DE3486261T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
DE84306928T 1983-11-10 1984-10-10 Speichermatrix. Expired - Fee Related DE3486261T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/551,736 US4574367A (en) 1983-11-10 1983-11-10 Memory cell and array

Publications (2)

Publication Number Publication Date
DE3486261D1 DE3486261D1 (de) 1994-02-10
DE3486261T2 true DE3486261T2 (de) 1994-04-28

Family

ID=24202465

Family Applications (2)

Application Number Title Priority Date Filing Date
DE84306928T Expired - Fee Related DE3486261T2 (de) 1983-11-10 1984-10-10 Speichermatrix.
DE198484306928T Pending DE142266T1 (de) 1983-11-10 1984-10-10 Speichermatrix.

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE198484306928T Pending DE142266T1 (de) 1983-11-10 1984-10-10 Speichermatrix.

Country Status (4)

Country Link
US (1) US4574367A (https=)
EP (1) EP0142266B1 (https=)
JP (1) JPS60115093A (https=)
DE (2) DE3486261T2 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4922411A (en) * 1988-12-27 1990-05-01 Atmel Corporation Memory cell circuit with supplemental current

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3487376A (en) * 1965-12-29 1969-12-30 Honeywell Inc Plural emitter semiconductive storage device
US3764825A (en) 1972-01-10 1973-10-09 R Stewart Active element memory
SU752490A1 (ru) * 1976-06-03 1980-07-30 Предприятие П/Я В-8466 Трехтактный регистр сдвига
US4151609A (en) * 1977-10-11 1979-04-24 Monolithic Memories, Inc. First in first out (FIFO) memory
JPS5564685A (en) * 1978-11-07 1980-05-15 Fujitsu Ltd Semiconductor memory unit

Also Published As

Publication number Publication date
DE142266T1 (de) 1986-03-20
US4574367A (en) 1986-03-04
EP0142266B1 (en) 1993-12-29
EP0142266A2 (en) 1985-05-22
JPS60115093A (ja) 1985-06-21
DE3486261D1 (de) 1994-02-10
EP0142266A3 (en) 1987-07-01
JPH0430678B2 (https=) 1992-05-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: VANTIS CORP.)N.D.GES.D.STAATES DELAWARE), SUNNYVAL

8339 Ceased/non-payment of the annual fee